CAL support on FPG-EYE

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== Introduction ==
== Introduction ==
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In this tutorial we will explain how to create a CAL's network inside the FPGA on Evidence board FPG-EYE.
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This tutorial explains how to create a [[Brief introduction to the CAL language | CAL]] network for the FPGA on the Evidence's FPG-EYE board using three system actors developed for the FPG-EYE board. Also, it explains how to integrate a hardware CAL network with our system actors.  For more background information, see the [[Brief introduction to the CAL language]].
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We will use some system ACTORS developed for the Evidence's board. We will explain how to integrate a hardware  
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network CAL with our system actors and how to synthesize the network in the FPG-EYE.
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== Prerequisites ==
== Prerequisites ==
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If you are starting to work with board FPG-EYE, in the first you have to download and install the right developer tools.  
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Before to start working with FPG-EYE board, you have to download and install the right developer tools.  
=== Eclipse ===
=== Eclipse ===
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The Eclipse is designed for building integrated development environments (IDEs). It can be used to create diverse end-to-end computing solutions for multiple execution environments. You can download it at [http://www.eclipse.org/ this web address].
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Eclipse is designed to build integrated development environments (IDEs). It can be used to create various end-to-end computing solutions for multiple execution environments. You can download it at [http://www.eclipse.org/ http://www.eclipse.org/].
=== OpenForge ===
=== OpenForge ===
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OpenForge is xlim to hdl compiler. You have the download at [https://openforge.svn.sourceforge.net/svnroot/openforge this web address].
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OpenForge is a XLIM to HDL compiler. You can download it at [https://openforge.svn.sourceforge.net/svnroot/openforge https://openforge.svn.sourceforge.net/svnroot/openforge].
=== OpenDf ===
=== OpenDf ===
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OpenDf is a CAL simulator and works as the front end for generation of HDL. The opendf tools can produce also intermediate format xlim.
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OpenDf is a CAL simulator working as the front end for HDL generation. The OpenDf tools can even produce XLIM code as intermediate format.
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Then you download [https://opendf.svn.sourceforge.net/svnroot/opendf opendf]. To install the plugins in the Eclipse you have to follow the instructions that you can find [https://opendf.svn.sourceforge.net/svnroot/opendf/trunk/doc/Eclipse_Plugin_Install.txt here].
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You can download it at [https://opendf.svn.sourceforge.net/svnroot/opendf https://opendf.svn.sourceforge.net/svnroot/opendf]. To install the plug-in in Eclipse you can follow [https://opendf.svn.sourceforge.net/svnroot/opendf/trunk/doc/Eclipse_Plugin_Install.txt these instructions on the OpendDf site].
=== ispLEVER ===
=== ispLEVER ===
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On Evidence's board is based on a Lattice FPGA device so you have to use Lattice developer tools for compiling CAL project. We used the [http://www.latticesemi.com/products/designsoftware/isplever/index.cfm ispLEVER] for our project. It is a integrated software environment that controls all aspects of development flow. There is a ispLEVER free version that can work with project the contain only Verilog or only VHDL files no together.  
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FPG-EYE board is based on a Lattice FPGA, so Lattice developer tools must be used to compile CAL projects. In this tutorial [http://www.latticesemi.com/products/designsoftware/isplever/index.cfm Lattice ispLEVER] is adopted. ispLEVER is an integrated software development environment able to control all aspects of the development work flow. It should be noticed that the free ispLEVER version cannot be used for this tutorial as it is able to compile project containing only either Verilog or VHDL source files.  
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Unfortunately, a CAL's project contains a mix of Verilog and VHDL files, so you need to buy from Lattice Semiconductor a license software.
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In order to be able to proceed with this tutorial you need a commercial license for ispLEVER from Lattice Semiconductor.
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=== FPG-EYE package ===
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=== Diamond ===
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The FPG-EYE package contains the system actors source files in Verilog (system actor Leds, system actor Switches and system actor Camera). There are also examples of using the system actor, test bench for simulations. The examples are ready to use, you must compile and try them on FPG-EYE.
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Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. A free version is available on [http://www.latticesemi.com/products/designsoftware/diamond/downloads.cfm download Lattice page]. A free license can be requested from the Lattice website previous Lattice site registration.
 +
It should be noticed that the free Diamond version cannot be used for this tutorial as it is able to compile project containing only either Verilog or VHDL source files.
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In order to be able to proceed with this tutorial you need a commercial license for Diamond from Lattice Semiconductor.
 +
 
 +
== FPG-EYE package ==
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The FPG-EYE package contains the system actors source files in Verilog for three actors (LEDs, Switches, and Camera), some examples their use, and  test bench to simulate each actor. To be used those examples have only to be compiled.
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== System Actors in FPG package ==
 
The system actors we have created for the FPG-EYE are:
The system actors we have created for the FPG-EYE are:
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* <tt>Actor Leds</tt>.
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* <tt>Leds</tt>.
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* <tt>Actor Switches</tt>.
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* <tt>Switches</tt>.
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* <tt>Actor Camera</tt>.
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* <tt>Camera</tt>.
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=== System Actor Leds ===
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=== LEDs System Actor ===
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The <tt>System Actor Leds</tt> is written in Verilog. The actor uses eight <tt>LEDs</tt> present on the boards (see <tt>DL0</tt>,...., <tt>DL7</tt> into <tt>ES-02610_SCH_main.pdf</tt> file).
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The <tt>LEDs System Actor</tt>, written in Verilog, uses the eight <tt>LEDs</tt> on the boards (see <tt>DL0</tt>,...., <tt>DL7</tt> into <tt>ES-02610_SCH_main.pdf</tt> file) to display the input byte.
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The Actor has got an input CAL compatible interface (it receives token from another Actor) with a data size of 8 bits, one bit for each leds (<tt>data_0 => led0</tt>, <tt>data_1 => led1</tt>, <tt>etc...</tt>). When a <tt>data_bit</tt> is 0 logic the corresponding <tt>LED</tt> is off, when a <tt>data_bit</tt> is 1 logic, the corresponding <tt>LED</tt> is on.
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The Actor input interface receives an 8 bit token from another actor in the system, one bit for each LEDs (<tt>data_0 => led0</tt>, <tt>data_1 => led1</tt>, <tt>etc...</tt>). When a <tt>data_bit</tt> is 0 the corresponding <tt>LED</tt> is off, when a <tt>data_bit</tt> is 1 logic, the corresponding <tt>LED</tt> is on.
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The actor <tt>Leds</tt> consists of the following files:
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The actor <tt>LEDs</tt> consists of the following files:
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* <tt>leds.v</tt> (in the directory <tt>svn-cal\hw\trunk\hdl_actors\actor_led</tt>)
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* <tt>LEDs.v</tt> (in the directory <tt>svn-cal\hw\trunk\hdl_actors\actor_led</tt>)
* <tt>arbiter2.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\arbiter2</tt>)
* <tt>arbiter2.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\arbiter2</tt>)
* <tt>serial_io.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\serial_io</tt>)
* <tt>serial_io.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\serial_io</tt>)
* <tt>wb_leds.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\examble1</tt>)
* <tt>wb_leds.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\examble1</tt>)
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[[File:leds.png|center|thumb|200px|System Actors Leds structure]]
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[[File:leds.png|center|thumb|200px|System Actors LEDs structure]]
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==== leds.v ====
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;leds.v
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In the <tt>leds.v</tt> file there is a state machine <tt>leds</tt> (written in Verilog) that manages on one side the <tt>Actors</tt> protocol,
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: The <tt>leds.v</tt> file contains the module <tt>leds</tt> (a state machine written in Verilog) that manages both the <tt>Actors</tt> protocol, and the <tt>WishBone</tt> bus protocol.
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and on the other side the <tt>WishBone</tt> bus protocol.
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==== arbiter2.v ====
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;arbiter2.v
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In the <tt>arbiter2.v</tt> file there is the module <tt>arbiter</tt> (written in Verilog). It's two way <tt>WishBone</tt> arbiter, two <tt>masters</tt> and a single <tt>slave</tt>. The actor <tt>leds</tt> uses the <tt>master bus 0</tt> (wb0) the actors switches uses the <tt>master bus 1</tt> (wb1).
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: The <tt>arbiter2.v</tt> file contains the <tt>arbiter</tt> module (written in Verilog), a two-way <tt>WishBone</tt> arbiter with two <tt>masters</tt> and a single <tt>slave</tt>. The actor <tt>LEDs</tt> uses the <tt>master bus 0</tt> (wb0), while the actors <tt>Switches</tt> uses the <tt>master bus 1</tt> (wb1).
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==== serial_io.v ====
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;serial_io.v
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In the file <tt>serial_io.v</tt> there is a state machine <tt>serial_io</tt> (written in Verilog) that manages on the one side the <tt>WishBone</tt> protocol, and on the other side a serial/parallel register, the <tt>74hc595</tt> chip. The <tt>74hc595</tt> drive the leds on the board.
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: The file <tt>serial_io.v</tt> contains a state machine <tt>serial_io</tt> (written in Verilog) managing the <tt>WishBone</tt> protocol, and a serial/parallel register, interfacing with the <tt>74hc595</tt> chip that drives the LEDs on the board.
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==== wb_leds.v ====
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;wb_leds.v
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The file <tt>wb_leds.v</tt> is a wrapper where there are present the component <tt>leds</tt>, <tt>arbiter</tt> and <tt>serial_io</tt> with their connections.
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:The file <tt>wb_leds.v</tt> is a wrapper enclosing the component <tt>leds</tt>, <tt>arbiter</tt> and <tt>serial_io</tt> as their connections.
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=== Example with System Actor Leds ===
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An example of these actors and the related component could be located in <tt>svn-cal\hw\trunk\examples\example1</tt>, where a simple testbench of the <tt>leds</tt> actor is present (<tt>example1\active_hdl</tt>). A project example based on an 8-bit number generator and the <tt>LEDs</tt> actor can be find in the directory <tt>svn-cal\hw\trunk\examples\example3</tt>.
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In the directory <tt>svn-cal\hw\trunk\examples\example1</tt> is present a simple testbench (<tt>example1\active_hdl</tt>) of the actor <tt>leds</tt>. There is also a IspLEVER project (<tt>example1\isp_lever</tt>).
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[[File:example3.png|center|thumb|200px|Example3: LEDs System Actor with eight bits number generator]]
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In the directory <tt>svn-cal\hw\trunk\examples\example3</tt> there is an example project with a eigth bits number generator with
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the actor <tt>leds</tt> (see fig. <tt>Example3</tt>).
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[[File:example3.png|center|thumb|200px|Example3: System Actor Leds with eight bits number generator]]
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=== Switches System Actor ===
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The <tt>Switches System Actor</tt> is an actor for the FPG-EYE board written in Verilog.
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=== System Actors Switches ===
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This actor uses eight Switches on the boards (see <tt>SW0</tt>,...., <tt>SW7</tt> into <tt>ES-02610_SCH_main.pdf</tt> file) to read their state, and produce a token containing such state.
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The <tt>System Actor Switches</tt> is an actor for the Evidence's board written in Verilog.
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The actor uses eight Switches on the boards (see <tt>SW0</tt>,...., <tt>SW7</tt> into <tt>ES-02610_SCH_main.pdf</tt> file).
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It has got an output CAL compatible interface (It sends token to another Actor) with a data size of 8 bits, one bit for each switches (<tt>data_0 => sw0</tt>, <tt>data_1 => sw1</tt>, <tt>etc...</tt>).
+
-
When a <tt>switch</tt> is pushed off its <tt>data bit</tt> is 0 logic, when a <tt>switch</tt> is pushed on its <tt>data bit</tt> is 1 logic.  
+
The actor <tt>Switches</tt> consists of the following files:
The actor <tt>Switches</tt> consists of the following files:
* <tt>switches.v</tt> (in the directory <tt>svn-cal\hw\trunk\hdl_actors\actor_switches</tt>)
* <tt>switches.v</tt> (in the directory <tt>svn-cal\hw\trunk\hdl_actors\actor_switches</tt>)
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* <tt>wb_switches.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\examble2</tt>)
* <tt>wb_switches.v</tt> (in the directory <tt>svn-cal\hw\trunk\examples\examble2</tt>)
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[[File:switches.png|center|thumb|200px|System Actors Switches structure]]
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[[File:switches.png|center|thumb|200px|Switches System Actors structure]]
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==== switches.v ====
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; switches.v
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In the <tt>switches.v</tt> file there is a state machine <tt>switches</tt> (written in Verilog) that manages on the one side the Actors's protocol,
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: The <tt>switches.v</tt> file consists of the state machine <tt>switches</tt> (written in Verilog) that manages both the Actors and the WishBone protocols.
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and on the other side the WishBone's bus protocol.
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-
==== arbiter2.v ====
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; arbiter2.v
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In the <tt>arbiter2.v</tt> file there is the module <tt>arbiter</tt> (written in Verilog). It's a two way <tt>WishBone</tt> arbiter, two <tt>masters</tt> and a single <tt>slave</tt>. The actor <tt>switches</tt> uses the <tt>master bus 1</tt> (wb1) the actors leds uses the <tt>master bus 0</tt> (wb0).
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: The <tt>arbiter2.v</tt> file contains the <tt>arbiter</tt> module (written in Verilog), a two-way <tt>WishBone</tt> arbiter with two <tt>masters</tt> and a single <tt>slave</tt>. The actor <tt>LEDs</tt> uses the <tt>master bus 0</tt> (wb0), while the actors <tt>Switches</tt> uses the <tt>master bus 1</tt> (wb1).
-
==== serial_io.v ====
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; serial_io.v
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In the file <tt>serial_io.v</tt> there is a state machine <tt>serial_io</tt> (written in Verilog) that manages on one side the <tt>WishBone</tt> protocol, and on the other a serial/parallel register, the <tt>74hc595</tt> chip. The <tt>74hc595</tt> drive the leds on the board.
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: The file <tt>serial_io.v</tt> contains a state machine <tt>serial_io</tt> (written in Verilog) managing the <tt>WishBone</tt> protocol, and a serial/parallel register, interfacing with the <tt>74hc595</tt> and <tt>74hc195</tt> chips that drive the LEDs and poll the switches.
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==== wb_switches.v ====
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; wb_switches.v
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The file <tt>wb_switches.v</tt> is a wrapper where there are present the component <tt>switches</tt>, <tt>arbiter</tt> and <tt>serial_io</tt> with their connections.
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: The file <tt>wb_switches.v</tt> is a wrapper enclosing the component <tt>switches</tt>, <tt>arbiter</tt> and <tt>serial_io</tt>.
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=== Example with System Actor Switches ===
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A simple testbench for this actors could be find in the directory <tt>svn-cal\hw\trunk\examples\example2</tt>.
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In the directory <tt>svn-cal\hw\trunk\examples\example2</tt> we stored a simple testbench (<tt>example2\active_hdl</tt>) of the actor <tt>switches</tt>. There is also a IspLEVER project (<tt>example2\isp_lever</tt>).
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Moreover, a simulation example where the actor <tt>switches</tt> is used along
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There is a simulation example, in the directory <tt>svn-cal\hw\trunk\examples\example4</tt>, where the actor <tt>switches</tt> is used along with the
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with the actor <tt>LEDs</tt> is contained in the directory
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actor <tt>leds</tt>. In this example when a switch is turned off/on its led is turned off/on (see fig: Example4).  
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<tt>svn-cal\hw\trunk\examples\example4</tt>. In this example, when a switch is
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In the directory <tt>svn-cal\hw\trunk\examples\example5</tt>, there is the previus component (example4) synthesized on FPGA Lattice.
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turned off/on the correspondent LED is turned off/on (see fig: Example4). The related Lattice FPGA implementation can be found in the <tt>svn-cal\hw\trunk\examples\example5</tt> directory.
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=== System Actors Camera ===
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The <tt>System Actor Camera</tt> is an actor for the Evidence's board written in Verilog. The actor uses a module <tt>camera</tt> can be placed on board (see <tt>ES-02310_SCH_camera.pdf</tt> file).
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 +
=== Camera System Actor ===
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The <tt>Camera System Actor</tt> is an actor for the FPG-EYE board written in
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Verilog. The actor require a hardware <tt>camera</tt> module to be mounted on
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the board.
[[File:camera.png|center|thumb|200px|System Actors camera structure]]
[[File:camera.png|center|thumb|200px|System Actors camera structure]]
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The actor <tt>Camera</tt> consists of the following files:
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The actor <tt>Camera</tt> consists only of the file <tt>act_camera.v</tt> (in the directory <tt>svn-cal\hw\trunk\hdl_actors\actor_camera</tt>)
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* <tt>act_camera.v</tt> (in the directory <tt>svn-cal\hw\trunk\hdl_actors\actor_camera</tt>)
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==== act_camera.v ====
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In the <tt>act_camera.v</tt> file there is a state machine <tt>camera</tt> (written in Verilog) that manages on the one side the camera signals
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and on the other side the CAL's protocol. The actor <tt>Camera</tt> has got two output CAL compatible interface (they send token to another actor). The first output CAL has got a data size of 8 bits and it sends token with image pixel value. The second output CAL has got a data size of 1 bit and it sends token when start a new frame.
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=== Example with System Actor Camera ===
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In the directory <tt>svn-cal\hw\trunk\examples\example7</tt> is present a simple example for actor <tt>camera>/tt> use. In the example are present
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the system actor <tt>camera</tt> and the system actor <tt>leds</tt>. For what concerns the example, the board LEDs are turned on or off proportionally to the average image luminance. In this demo we have used two outputs for the camera, the first one providing a token whenever a frame starts and the second one providing the image data pixel by pixel.
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[[File:example7.png|center|thumb|200px|example7: Board Leds are turned on or off proportionally to the average image luminance]]
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== How to create a CAL project under ispLEVER ==
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For now, if you want to use our system actors in your project, you have to modify some automatically generated CAL files.
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Our system actors aren't still included in OpenForge, so after you synthese your CAL design you have to enter manually the system actors files.
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To do this you must create a wrapper to a higher level.
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Here following is a complete design procedure for Lattice FPGAs:
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*  You must get the ispLEVER from Lattice semiconductors. The free version can work just with Verilog or VHDL files never togheter. Unfortunately in the Cal project we have a mix Verilog and VHDL files. So you have to buy a license.
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* Once opened ispLEVER you click on new project.
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+
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[[File:new_project.png|center|thumb|200px| Click on "Open Project"]]
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+
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* In the next windows you can choose the project name and the its destination in the file system.
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For the options "Design Entry Type" select "Mixed Verilog/VHDL"
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-
 
+
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[[File:name_project.png|center|thumb|200px|Add "Name Project"]]
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+
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* Tn the next windows you must select the device. You must select these value:
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** Family: LatticeXP2,
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** Device: LFXP2-17E,
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** Speed grade: 5,
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** Package type: PQFP208,
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** Operating conditions: Commercial,
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** PartName: LFXP2-17E-5QN208C
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-
 
+
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[[File:select_device.png|center|thumb|200px|"Select Device"]]
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-
 
+
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* The next windows is "Add Source". Click on End button.
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-
 
+
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[[File:add_source.png|center|thumb|200px|"Add Source"]]
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+
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* Now you should see the following figure:
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[[File:isp_lever.png|center|thumb|200px|ispLEVER]]
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* Now you have to import the library <tt>lattice_cal.vhdl</tt> (<tt>svn-cal/hw/trunk/lib_vhdl</tt>). Click right buttom on device e select "Import...".
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+
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[[File:import_file.png|center|thumb|200px|Import file]]
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* Now select the file <tt>lattice_cal.vhdl</tt>
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[[File:lib_vhdl.png|center|thumb|200px|Import the file "lattice_cal.vhdl"]]
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* Now click with right mouse buttom the lattice_cal.vhdl and select "Library Name"
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; act_camera.v
 +
: The <tt>act_camera.v</tt> file consists of the state machine <tt>camera</tt> (written in Verilog) that manages the camera signals and the CAL protocol. The actor <tt>Camera</tt> has two CAL compatible output interfaces (sending tokens to other actors). The first CAL output has a data size of 8 bits and sends token containing the image pixel values, while the second CAL output, with a data size of 1 bit, sends a token whenever a new frame starts.
-
[[File:library_name.png|center|thumb|200px|Select "Library Name"]]
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A simple example for <tt>camera</tt> actor is located in the <tt>svn-cal\hw\trunk\examples\example7</tt> directory. All the three actors are used in this example: the LEDs act as a bar graph, whose length is proportional to the average image luminance.
 +
[[File:example7.png|center|thumb|200px|example7: Board LEDs are turned on or off proportionally to the average image luminance]]
-
* In the Box "VHDL Library Name" insert the namespace <tt>SystemBuilder</tt>
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== How to Interface a CAL Netlist to System Actors ==
 +
To interface a CAL Netlist with an actor few steps are needed:
 +
* Create a Netlist in the CAL environment with the needed number of input and output ports
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* Build a wrapper in Verilog (or VHDL) that connects the netlist with the required system actors
-
[[File:system_builder.png|center|thumb|200px|Write: SystemBuilder]]
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== How to Build a CAL Project with ispLEVER or Diamond ==
 +
First you must to have a Cal project with System Actors for FPG-EYE. See [[Create a Cal project with System Actors]] for instructions on how to do it.
 +
To build an ispLEVER CAL project we have to:
 +
* Open ispLEVER and click on new project. [[File:new_project.png|center|thumb|200px| Click on "Open Project"]]
 +
* In the following window choose the project name and the its destination path. Please remember to select "Mixed Verilog/VHDL" for the option "Design Entry Type". [[File:name_project.png|center|thumb|200px|Add "Name Project"]]
 +
* In the following window we have to select the device. For the FPG-EYE board we must use:
 +
** Family: LatticeXP2;
 +
** Device: LFXP2-17E;
 +
** Speed grade: 5;
 +
** Package type: PQFP208;
 +
** Operating conditions: Commercial;
 +
** PartName: LFXP2-17E-5QN208C. [[File:select_device.png|center|thumb|200px|"Select Device"]]
 +
* Finally by clicking the End button [[File:add_source.png|center|thumb|200px|"Add Source"]] the following window will be displayed: [[File:isp_lever.png|center|thumb|200px|ispLEVER]]
 +
* To import <tt>lattice_cal.vhdl</tt> the library (<tt>svn-cal/hw/trunk/lib_vhdl</tt>) we have to right click on device and select "Import...". [[File:import_file.png|center|thumb|200px|Import file]]
 +
* In the file window we can now select the file <tt>lattice_cal.vhdl</tt> [[File:lib_vhdl.png|center|thumb|200px|Import the file "lattice_cal.vhdl"]]
 +
* Now by right clicking the lattice_cal.vhdl we can select "Library Name" [[File:library_name.png|center|thumb|200px|Select "Library Name"]]
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* In the Box "VHDL Library Name" we can insert the namespace <tt>SystemBuilder</tt>[[File:system_builder.png|center|thumb|200px|Write: SystemBuilder]]
 +
* Each file created by the CAL compiler has an undefined module FD. This module is a D-FF (flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. You have to remove this part because the Lattice software does not recognize it.<br/> There is a Perl script <tt>main_modify.pl</tt> that searches these FD instances in Verilog files and replaces them with a reset synchronizer. You can run this Perl script with the top level VHDL file as input. Before executing the Perl script, please check that all generated files are in the same folder. If the top level generated file name is <tt>main_nw.vhd</tt>, we can issue <tt>perl main_modify.pl main_nw</tt>.<br/> The script will produce a *_mod.v file for each parsed Verilog file.
 +
* After importing the files related to the various actors (LED, camera, and those related to our CAL netlist), a constraint file describing the connection between FPGA pins and logic blocks must be created. An example of these constraints can be found in "svn-cal\hw\trunk\examples\example7\isp_lever\example7.lpf"
 +
* We can finally compile the project, thus obtaining a binary JED file to program the FPG-EYE board.
-
* Each file created by Cal has an undefined module FD. This module is a D-FF(flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. Yuo have to remove this part because the Lattice software does not recognize it. There is a Perl script <tt>main_modify.pl</tt> that search and remove these FD instances in verilog and replace them with a reset synchronizer. You can run this perl script with top level VHD file as input. Please make sure that all generated files be in the same folder.
+
== How to Build a CAL Project with Diamond ==
-
For example: if your top level generated file name is <tt>main_nw.vhd</tt>
+
First you must to have a Cal project with System Actors for FPG-EYE. See [[Create a Cal project with System Actors]] for instructions on how to do it.
-
Then run : <tt>perl main_modify.pl main_nw</tt>
+
To build a Diamond CAL project we have to:
-
After running the script, it will generate *_mod.v files for each verilog files. You can use that one.
+
* Open Diamond and click on new project. [[File:new_project_diamond.png|center|thumb|200px| Click on "Open Project"]]
 +
* In the following window choose the project name and the its destination path.[[File:name_project_diamond.png|center|thumb|200px|Add "Name Project"]]
 +
* In the following window we have to select the device. For the FPG-EYE board we must use:
 +
** Family: LatticeXP2;
 +
** Device: LFXP2-17E;
 +
** Speed grade: 5;
 +
** Package type: PQFP208;
 +
** Operating conditions: Commercial;
 +
** PartName: LFXP2-17E-5QN208C. [[File:select_device_diamond.png|center|thumb|200px|"Select Device"]]
 +
* Finally by clicking the End button the following window will be displayed: [[File:diamond.png|center|thumb|200px|Diamond]]
 +
* To import <tt>lattice_cal.vhdl</tt> the library (<tt>svn-cal/hw/trunk/lib_vhdl</tt>) we have to right click on device and select "Add->Existing File". [[File:import_file_diamond.png|center|thumb|200px|Import file]]
 +
* In the file window we can now select the file <tt>lattice_cal.vhdl</tt> [[File:lib_vhdl.png|center|thumb|200px|Import the file "lattice_cal.vhdl"]]
 +
* Now by right clicking the lattice_cal.vhdl we can select "Properties" an then in the Box "VHDL Library Name" we can insert the namespace <tt>SystemBuilder</tt>[[File:system_builder_diamond.png|center|thumb|200px|Write: SystemBuilder]]
 +
* Each file created by the CAL compiler has an undefined module FD. This module is a D-FF (flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. You have to remove this part because the Lattice software does not recognize it.<br/> There is a Perl script <tt>main_modify.pl</tt> that searches these FD instances in Verilog files and replaces them with a reset synchronizer. You can run this Perl script with the top level VHDL file as input. Before executing the Perl script, please check that all generated files are in the same folder. If the top level generated file name is <tt>main_nw.vhd</tt>, we can issue <tt>perl main_modify.pl main_nw</tt>.<br/> The script will produce a *_mod.v file for each parsed Verilog file.
 +
* After importing the files related to the various actors (LED, camera, and those related to our CAL netlist), a constraint file describing the connection between FPGA pins and logic blocks must be created. An example of these constraints can be found in "svn-cal\hw\trunk\examples\example7\diamond\example7.lpf"
 +
* We can finally compile the project, thus obtaining a binary JED file to program the FPG-EYE board.
 +
[[File:compile_diamond.png|center|thumb|200px| "Return All" for obtaining a binary JED file]]
-
* Remenber that if you want to use our System Actor (leds, switches and camera) you have to create a file wripper (in Verilog or VHDL) where
+
== How to Program the FPG-EYE board ==
-
you put the system actors with the CAL generated file). A good example is the <tt>example7</tt> (<tt>svn-cal\hw\trunk\examples\example7</tt>)
+
See [[Programming the FPG-EYE board]] for instructions on how to download the JED file onto the board

Latest revision as of 16:00, 14 November 2011

Contents

Introduction

This tutorial explains how to create a CAL network for the FPGA on the Evidence's FPG-EYE board using three system actors developed for the FPG-EYE board. Also, it explains how to integrate a hardware CAL network with our system actors. For more background information, see the Brief introduction to the CAL language.

Prerequisites

Before to start working with FPG-EYE board, you have to download and install the right developer tools.

Eclipse

Eclipse is designed to build integrated development environments (IDEs). It can be used to create various end-to-end computing solutions for multiple execution environments. You can download it at http://www.eclipse.org/.

OpenForge

OpenForge is a XLIM to HDL compiler. You can download it at https://openforge.svn.sourceforge.net/svnroot/openforge.

OpenDf

OpenDf is a CAL simulator working as the front end for HDL generation. The OpenDf tools can even produce XLIM code as intermediate format. You can download it at https://opendf.svn.sourceforge.net/svnroot/opendf. To install the plug-in in Eclipse you can follow these instructions on the OpendDf site.

ispLEVER

FPG-EYE board is based on a Lattice FPGA, so Lattice developer tools must be used to compile CAL projects. In this tutorial Lattice ispLEVER is adopted. ispLEVER is an integrated software development environment able to control all aspects of the development work flow. It should be noticed that the free ispLEVER version cannot be used for this tutorial as it is able to compile project containing only either Verilog or VHDL source files. In order to be able to proceed with this tutorial you need a commercial license for ispLEVER from Lattice Semiconductor.

Diamond

Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. A free version is available on download Lattice page. A free license can be requested from the Lattice website previous Lattice site registration. It should be noticed that the free Diamond version cannot be used for this tutorial as it is able to compile project containing only either Verilog or VHDL source files. In order to be able to proceed with this tutorial you need a commercial license for Diamond from Lattice Semiconductor.

FPG-EYE package

The FPG-EYE package contains the system actors source files in Verilog for three actors (LEDs, Switches, and Camera), some examples their use, and test bench to simulate each actor. To be used those examples have only to be compiled.

The system actors we have created for the FPG-EYE are:

  • Leds.
  • Switches.
  • Camera.

LEDs System Actor

The LEDs System Actor, written in Verilog, uses the eight LEDs on the boards (see DL0,...., DL7 into ES-02610_SCH_main.pdf file) to display the input byte. The Actor input interface receives an 8 bit token from another actor in the system, one bit for each LEDs (data_0 => led0, data_1 => led1, etc...). When a data_bit is 0 the corresponding LED is off, when a data_bit is 1 logic, the corresponding LED is on. The actor LEDs consists of the following files:

  • LEDs.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_led)
  • arbiter2.v (in the directory svn-cal\hw\trunk\examples\arbiter2)
  • serial_io.v (in the directory svn-cal\hw\trunk\examples\serial_io)
  • wb_leds.v (in the directory svn-cal\hw\trunk\examples\examble1)
System Actors LEDs structure
leds.v
The leds.v file contains the module leds (a state machine written in Verilog) that manages both the Actors protocol, and the WishBone bus protocol.
arbiter2.v
The arbiter2.v file contains the arbiter module (written in Verilog), a two-way WishBone arbiter with two masters and a single slave. The actor LEDs uses the master bus 0 (wb0), while the actors Switches uses the master bus 1 (wb1).
serial_io.v
The file serial_io.v contains a state machine serial_io (written in Verilog) managing the WishBone protocol, and a serial/parallel register, interfacing with the 74hc595 chip that drives the LEDs on the board.
wb_leds.v
The file wb_leds.v is a wrapper enclosing the component leds, arbiter and serial_io as their connections.

An example of these actors and the related component could be located in svn-cal\hw\trunk\examples\example1, where a simple testbench of the leds actor is present (example1\active_hdl). A project example based on an 8-bit number generator and the LEDs actor can be find in the directory svn-cal\hw\trunk\examples\example3.

Example3: LEDs System Actor with eight bits number generator

Switches System Actor

The Switches System Actor is an actor for the FPG-EYE board written in Verilog. This actor uses eight Switches on the boards (see SW0,...., SW7 into ES-02610_SCH_main.pdf file) to read their state, and produce a token containing such state. The actor Switches consists of the following files:

  • switches.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_switches)
  • arbiter2.v (in the directory svn-cal\hw\trunk\examples\arbiter2)
  • serial_io.v (in the directory svn-cal\hw\trunk\examples\serial_io)
  • wb_switches.v (in the directory svn-cal\hw\trunk\examples\examble2)
Switches System Actors structure
switches.v
The switches.v file consists of the state machine switches (written in Verilog) that manages both the Actors and the WishBone protocols.
arbiter2.v
The arbiter2.v file contains the arbiter module (written in Verilog), a two-way WishBone arbiter with two masters and a single slave. The actor LEDs uses the master bus 0 (wb0), while the actors Switches uses the master bus 1 (wb1).
serial_io.v
The file serial_io.v contains a state machine serial_io (written in Verilog) managing the WishBone protocol, and a serial/parallel register, interfacing with the 74hc595 and 74hc195 chips that drive the LEDs and poll the switches.
wb_switches.v
The file wb_switches.v is a wrapper enclosing the component switches, arbiter and serial_io.

A simple testbench for this actors could be find in the directory svn-cal\hw\trunk\examples\example2. Moreover, a simulation example where the actor switches is used along with the actor LEDs is contained in the directory svn-cal\hw\trunk\examples\example4. In this example, when a switch is turned off/on the correspondent LED is turned off/on (see fig: Example4). The related Lattice FPGA implementation can be found in the svn-cal\hw\trunk\examples\example5 directory.

Camera System Actor

The Camera System Actor is an actor for the FPG-EYE board written in Verilog. The actor require a hardware camera module to be mounted on the board.

System Actors camera structure

The actor Camera consists only of the file act_camera.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_camera)

act_camera.v
The act_camera.v file consists of the state machine camera (written in Verilog) that manages the camera signals and the CAL protocol. The actor Camera has two CAL compatible output interfaces (sending tokens to other actors). The first CAL output has a data size of 8 bits and sends token containing the image pixel values, while the second CAL output, with a data size of 1 bit, sends a token whenever a new frame starts.

A simple example for camera actor is located in the svn-cal\hw\trunk\examples\example7 directory. All the three actors are used in this example: the LEDs act as a bar graph, whose length is proportional to the average image luminance.

example7: Board LEDs are turned on or off proportionally to the average image luminance

How to Interface a CAL Netlist to System Actors

To interface a CAL Netlist with an actor few steps are needed:

  • Create a Netlist in the CAL environment with the needed number of input and output ports
  • Build a wrapper in Verilog (or VHDL) that connects the netlist with the required system actors

How to Build a CAL Project with ispLEVER or Diamond

First you must to have a Cal project with System Actors for FPG-EYE. See Create a Cal project with System Actors for instructions on how to do it. To build an ispLEVER CAL project we have to:

  • Open ispLEVER and click on new project.
    Click on "Open Project"
  • In the following window choose the project name and the its destination path. Please remember to select "Mixed Verilog/VHDL" for the option "Design Entry Type".
    Add "Name Project"
  • In the following window we have to select the device. For the FPG-EYE board we must use:
    • Family: LatticeXP2;
    • Device: LFXP2-17E;
    • Speed grade: 5;
    • Package type: PQFP208;
    • Operating conditions: Commercial;
    • PartName: LFXP2-17E-5QN208C.
      "Select Device"
  • Finally by clicking the End button
    "Add Source"
    the following window will be displayed:
    ispLEVER
  • To import lattice_cal.vhdl the library (svn-cal/hw/trunk/lib_vhdl) we have to right click on device and select "Import...".
    Import file
  • In the file window we can now select the file lattice_cal.vhdl
    Import the file "lattice_cal.vhdl"
  • Now by right clicking the lattice_cal.vhdl we can select "Library Name"
    Select "Library Name"
  • In the Box "VHDL Library Name" we can insert the namespace SystemBuilder
    Write: SystemBuilder
  • Each file created by the CAL compiler has an undefined module FD. This module is a D-FF (flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. You have to remove this part because the Lattice software does not recognize it.
    There is a Perl script main_modify.pl that searches these FD instances in Verilog files and replaces them with a reset synchronizer. You can run this Perl script with the top level VHDL file as input. Before executing the Perl script, please check that all generated files are in the same folder. If the top level generated file name is main_nw.vhd, we can issue perl main_modify.pl main_nw.
    The script will produce a *_mod.v file for each parsed Verilog file.
  • After importing the files related to the various actors (LED, camera, and those related to our CAL netlist), a constraint file describing the connection between FPGA pins and logic blocks must be created. An example of these constraints can be found in "svn-cal\hw\trunk\examples\example7\isp_lever\example7.lpf"
  • We can finally compile the project, thus obtaining a binary JED file to program the FPG-EYE board.

How to Build a CAL Project with Diamond

First you must to have a Cal project with System Actors for FPG-EYE. See Create a Cal project with System Actors for instructions on how to do it. To build a Diamond CAL project we have to:

  • Open Diamond and click on new project.
    Click on "Open Project"
  • In the following window choose the project name and the its destination path.
    Add "Name Project"
  • In the following window we have to select the device. For the FPG-EYE board we must use:
    • Family: LatticeXP2;
    • Device: LFXP2-17E;
    • Speed grade: 5;
    • Package type: PQFP208;
    • Operating conditions: Commercial;
    • PartName: LFXP2-17E-5QN208C.
      "Select Device"
  • Finally by clicking the End button the following window will be displayed:
    Diamond
  • To import lattice_cal.vhdl the library (svn-cal/hw/trunk/lib_vhdl) we have to right click on device and select "Add->Existing File".
    Import file
  • In the file window we can now select the file lattice_cal.vhdl
    Import the file "lattice_cal.vhdl"
  • Now by right clicking the lattice_cal.vhdl we can select "Properties" an then in the Box "VHDL Library Name" we can insert the namespace SystemBuilder
    Write: SystemBuilder
  • Each file created by the CAL compiler has an undefined module FD. This module is a D-FF (flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. You have to remove this part because the Lattice software does not recognize it.
    There is a Perl script main_modify.pl that searches these FD instances in Verilog files and replaces them with a reset synchronizer. You can run this Perl script with the top level VHDL file as input. Before executing the Perl script, please check that all generated files are in the same folder. If the top level generated file name is main_nw.vhd, we can issue perl main_modify.pl main_nw.
    The script will produce a *_mod.v file for each parsed Verilog file.
  • After importing the files related to the various actors (LED, camera, and those related to our CAL netlist), a constraint file describing the connection between FPGA pins and logic blocks must be created. An example of these constraints can be found in "svn-cal\hw\trunk\examples\example7\diamond\example7.lpf"
  • We can finally compile the project, thus obtaining a binary JED file to program the FPG-EYE board.
"Return All" for obtaining a binary JED file

How to Program the FPG-EYE board

See Programming the FPG-EYE board for instructions on how to download the JED file onto the board

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