CAL support on FPG-EYE

From ErikaWiki

Revision as of 19:17, 15 February 2011 by Salva (Talk | contribs)
Jump to: navigation, search

Contents

Introduction

In this tutorial we will explain how to create a CAL's network inside the FPGA on Evidence board FPG-EYE. We will use some system ACTORS developed for the Evidence's board. We will explain how to integrate a hardware network CAL with our system actors and how to synthesize the network in the FPG-EYE.

Prerequisites

If you are starting to work with board FPG-EYE, in the first you have to download and install the right developer tools.

Eclipse

The Eclipse is designed for building integrated development environments (IDEs). It can be used to create diverse end-to-end computing solutions for multiple execution environments. You can download it at this web address.

OpenForge

OpenForge is xlim to hdl compiler. You have the download at this web address.

OpenDf

OpenDf is a CAL simulator and works as the front end for generation of HDL. The opendf tools can produce also intermediate format xlim. Then you download opendf. To install the plugins in the Eclipse you have to follow the instructions that you can find here.

ispLEVER

On Evidence's board is based on a Lattice FPGA device so you have to use Lattice developer tools for compiling CAL project. We used the ispLEVER for our project. It is a integrated software environment that controls all aspects of development flow. There is a ispLEVER free version that can work with project the contain only Verilog or only VHDL files no together. Unfortunately, a CAL's project contains a mix of Verilog and VHDL files, so you need to buy from Lattice Semiconductor a license software.

System Actors

The system actors we have created for the FPG-EYE are:

  • Actor Leds.
  • Actor Switches.
  • Actor Camera.

System Actor Leds

The System Actor Leds is written in Verilog. The actor uses eight LEDs present on the boards (see DL0,...., DL7 into ES-02610_SCH_main.pdf file). The Actor has got an input CAL compatible interface (it receives token from another Actor) with a data size of 8 bits, one bit for each leds (data_0 => led0, data_1 => led1, etc...). When a data_bit is 0 logic the corresponding LED is off, when a data_bit is 1 logic, the corresponding LED is on. The actor Leds consists of the following files:

  • leds.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_led)
  • arbiter2.v (in the directory svn-cal\hw\trunk\examples\arbiter2)
  • serial_io.v (in the directory svn-cal\hw\trunk\examples\serial_io)
  • wb_leds.v (in the directory svn-cal\hw\trunk\examples\examble1)
System Actors Leds structure

leds.v

In the leds.v file there is a state machine leds (written in Verilog) that manages on one side the Actors protocol, and on the other side the WishBone bus protocol.

arbiter2.v

In the arbiter2.v file there is the module arbiter (written in Verilog). It's two way WishBone arbiter, two masters and a single slave. The actor leds uses the master bus 0 (wb0) the actors switches uses the master bus 1 (wb1).

serial_io.v

In the file serial_io.v there is a state machine serial_io (written in Verilog) that manages on the one side the WishBone protocol, and on the other side a serial/parallel register, the 74hc595 chip. The 74hc595 drive the leds on the board.

wb_leds.v

The file wb_leds.v is a wrapper where there are present the component leds, arbiter and serial_io with their connections.

Example with System Actor Leds

In the directory svn-cal\hw\trunk\examples\example1 is present a simple testbench (example1\active_hdl) of the actor leds. There is also a IspLEVER project (example1\isp_lever). In the directory svn-cal\hw\trunk\examples\example3 there is an example project with a eigth bits number generator with the actor leds (see fig. Example3).

Example3: System Actor Leds with eight bits number generator

System Actors Switches

The System Actor Switches is an actor for the Evidence's board written in Verilog. The actor uses eight Switches on the boards (see SW0,...., SW7 into ES-02610_SCH_main.pdf file). It has got an output CAL compatible interface (It sends token to another Actor) with a data size of 8 bits, one bit for each switches (data_0 => sw0, data_1 => sw1, etc...). When a switch is pushed off its data bit is 0 logic, when a switch is pushed on its data bit is 1 logic. The actor Switches consists of the following files:

  • switches.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_switches)
  • arbiter2.v (in the directory svn-cal\hw\trunk\examples\arbiter2)
  • serial_io.v (in the directory svn-cal\hw\trunk\examples\serial_io)
  • wb_switches.v (in the directory svn-cal\hw\trunk\examples\examble2)
System Actors Switches structure

switches.v

In the switches.v file there is a state machine switches (written in Verilog) that manages on the one side the Actors's protocol, and on the other side the WishBone's bus protocol.

arbiter2.v

In the arbiter2.v file there is the module arbiter (written in Verilog). It's a two way WishBone arbiter, two masters and a single slave. The actor switches uses the master bus 1 (wb1) the actors leds uses the master bus 0 (wb0).

serial_io.v

In the file serial_io.v there is a state machine serial_io (written in Verilog) that manages on one side the WishBone protocol, and on the other a serial/parallel register, the 74hc595 chip. The 74hc595 drive the leds on the board.

wb_switches.v

The file wb_switches.v is a wrapper where there are present the component switches, arbiter and serial_io with their connections.

Example with System Actor Switches

In the directory svn-cal\hw\trunk\examples\example2 we stored a simple testbench (example2\active_hdl) of the actor switches. There is also a IspLEVER project (example2\isp_lever). There is a simulation example, in the directory svn-cal\hw\trunk\examples\example4, where the actor switches is used along with the actor leds. In this example when a switch is turned off/on its led is turned off/on (see fig: Example4). In the directory svn-cal\hw\trunk\examples\example5, there is the previus component (example4) synthesized on FPGA Lattice.

System Actors Camera

The System Actor Camera is an actor for the Evidence's board written in Verilog. The actor uses a module camera can be placed on board (see ES-02310_SCH_camera.pdf file).

System Actors camera structure

The actor Camera consists of the following files:

  • act_camera.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_camera)

act_camera.v

In the act_camera.v file there is a state machine camera (written in Verilog) that manages on the one side the camera signals and on the other side the CAL's protocol. The actor Camera has got two output CAL compatible interface (they send token to another actor). The first output CAL has got a data size of 8 bits and it sends token with image pixel value. The second output CAL has got a data size of 1 bit and it sends token when start a new frame.

Example with System Actor Camera

In the directory svn-cal\hw\trunk\examples\example7 is present a simple example for actor camera>/tt> use. In the example are present the system actor <tt>camera and the system actor leds. For what concerns the example, the board LEDs are turned on or off proportionally to the average image luminance. In this demo we have used two outputs for the camera, the first one providing a token whenever a frame starts and the second one providing the image data pixel by pixel.

example7: Board Leds are turned on or off proportionally to the average image luminance

How to create a CAL project under ispLEVER

For now, if you want to use our system actors in your project, you have to modify some automatically generated CAL files. Our system actors aren't still included in OpenForge, so after you synthese your CAL design you have to enter manually the system actors files. To do this you must create a wrapper to a higher level. Here following is a complete design procedure for Lattice FPGAs:

  • You must get the ispLEVER from Lattice semiconductors. The free version can work just with Verilog or VHDL files never togheter. Unfortunately in the Cal project we have a mix Verilog and VHDL files. So you have to buy a license.
  • Once opened ispLEVER you click on new project.
Click on "Open Project"
  • In the next windows you can choose the project name and the its destination in the file system.

For the options "Design Entry Type" select "Mixed Verilog/VHDL"

Add "Name Project"
  • Tn the next windows you must select the device. You must select these value:
    • Family: LatticeXP2,
    • Device: LFXP2-17E,
    • Speed grade: 5,
    • Package type: PQFP208,
    • Operating conditions: Commercial,
    • PartName: LFXP2-17E-5QN208C
"Select Device"
  • The next windows is "Add Source". Click on End button.
"Add Source"
  • Now you should see the following figure:
ispLEVER
  • Now you have to import the library lattice_cal.vhdl (svn-cal/hw/trunk/lib_vhdl). Click right buttom on device e select "Import...".
Import file
  • Now select the file lattice_cal.vhdl
Import the file "lattice_cal.vhdl"
  • Now click with right mouse buttom the lattice_cal.vhdl and select "Library Name"
Select "Library Name"
  • In the Box "VHDL Library Name" insert the namespace SystemBuilder
Write: SystemBuilder
  • Each file created by Cal has an undefined module FD. This module is a D-FF(flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. Yuo have to remove this part because the Lattice software does not recognize it. There is a Perl script main_modify.pl that search and remove these FD instances in verilog and replace them with a reset synchronizer. You can run this perl script with top level VHD file as input. Please make sure that all generated files be in the same folder.

For example: if your top level generated file name is main_nw.vhd Then run : perl main_modify.pl main_nw After running the script, it will generate *_mod.v files for each verilog files. You can use that one.

  • Remenber that if you want to use our System Actor (leds, switches and camera) you have to create a file wripper (in Verilog or VHDL) where

you put the system actors with the CAL generated file). A good example is the example7 (svn-cal\hw\trunk\examples\example7)

Personal tools