CAL support on FPG-EYE

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Contents

Introduction

This tutorial explains how to create a CAL network for the FPGA on the Evidence's FPG-EYE board using three system actors developed for the FPG-EYE board. Also, it explains how to integrate a hardware CAL network with our system actors. For more background information, see the Brief introduction to the CAL language.

Prerequisites

Before to start working with FPG-EYE board, you have to download and install the right developer tools.

Eclipse

Eclipse is designed to build integrated development environments (IDEs). It can be used to create various end-to-end computing solutions for multiple execution environments. You can download it at http://www.eclipse.org/.

OpenForge

OpenForge is a XLIM to HDL compiler. You can download it at https://openforge.svn.sourceforge.net/svnroot/openforge.

OpenDf

OpenDf is a CAL simulator working as the front end for HDL generation. The OpenDf tools can even produce XLIM code as intermediate format. You can download it at https://opendf.svn.sourceforge.net/svnroot/opendf. To install the plug-in in Eclipse you can follow these instructions on the OpendDf site.

ispLEVER

FPG-EYE board is based on a Lattice FPGA, so Lattice developer tools must be used to compile CAL projects. In this tutorial Lattice ispLEVER is adopted. ispLEVER is an integrated software development environment able to control all aspects of the development work flow. It should be noticed that the free ispLEVER version cannot be used for this tutorial as it is able to compile project containing only either Verilog or VHDL source files. In order to be able to proceed with this tutorial you need a commercial license for ispLEVER from Lattice Semiconductor.

FPG-EYE package

The FPG-EYE package contains the system actors source files in Verilog for three actors (LEDs, Switches, and Camera), some examples their use, and test bench to simulate each actor. To be used those examples have only to be compiled.

The system actors we have created for the FPG-EYE are:

  • Leds.
  • Switches.
  • Camera.

LEDs System Actor

The LEDs System Actor, written in Verilog, uses the eight LEDs on the boards (see DL0,...., DL7 into ES-02610_SCH_main.pdf file) to display the input byte. The Actor input interface receives an 8 bit token from another actor in the system, one bit for each LEDs (data_0 => led0, data_1 => led1, etc...). When a data_bit is 0 the corresponding LED is off, when a data_bit is 1 logic, the corresponding LED is on. The actor LEDs consists of the following files:

  • LEDs.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_led)
  • arbiter2.v (in the directory svn-cal\hw\trunk\examples\arbiter2)
  • serial_io.v (in the directory svn-cal\hw\trunk\examples\serial_io)
  • wb_leds.v (in the directory svn-cal\hw\trunk\examples\examble1)
System Actors LEDs structure
leds.v
The leds.v file contains the module leds (a state machine written in Verilog) that manages both the Actors protocol, and the WishBone bus protocol.
arbiter2.v
The arbiter2.v file contains the arbiter module (written in Verilog), a two-way WishBone arbiter with two masters and a single slave. The actor LEDs uses the master bus 0 (wb0), while the actors Switches uses the master bus 1 (wb1).
serial_io.v
The file serial_io.v contains a state machine serial_io (written in Verilog) managing the WishBone protocol, and a serial/parallel register, interfacing with the 74hc595 chip that drives the LEDs on the board.
wb_leds.v
The file wb_leds.v is a wrapper enclosing the component leds, arbiter and serial_io as their connections.

An example of these actors and the related component could be located in svn-cal\hw\trunk\examples\example1, where a simple testbench of the leds actor is present (example1\active_hdl). A project example based on an 8-bit number generator and the LEDs actor can be find in the directory svn-cal\hw\trunk\examples\example3.

Example3: LEDs System Actor with eight bits number generator

Switches System Actor

The Switches System Actor is an actor for the FPG-EYE board written in Verilog. This actor uses eight Switches on the boards (see SW0,...., SW7 into ES-02610_SCH_main.pdf file) to read their state, and produce a token containing such state. The actor Switches consists of the following files:

  • switches.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_switches)
  • arbiter2.v (in the directory svn-cal\hw\trunk\examples\arbiter2)
  • serial_io.v (in the directory svn-cal\hw\trunk\examples\serial_io)
  • wb_switches.v (in the directory svn-cal\hw\trunk\examples\examble2)
Switches System Actors structure
switches.v
The switches.v file consists of the state machine switches (written in Verilog) that manages both the Actors and the WishBone protocols.
arbiter2.v
The arbiter2.v file contains the arbiter module (written in Verilog), a two-way WishBone arbiter with two masters and a single slave. The actor LEDs uses the master bus 0 (wb0), while the actors Switches uses the master bus 1 (wb1).
serial_io.v
The file serial_io.v contains a state machine serial_io (written in Verilog) managing the WishBone protocol, and a serial/parallel register, interfacing with the 74hc595 and 74hc195 chips that drive the LEDs and poll the switches.
wb_switches.v
The file wb_switches.v is a wrapper enclosing the component switches, arbiter and serial_io.

A simple testbench for this actors could be find in the directory svn-cal\hw\trunk\examples\example2. Moreover, a simulation example where the actor switches is used along with the actor LEDs is contained in the directory svn-cal\hw\trunk\examples\example4. In this example, when a switch is turned off/on the correspondent LED is turned off/on (see fig: Example4). The related Lattice FPGA implementation can be found in the svn-cal\hw\trunk\examples\example5 directory.

Camera System Actor

The Camera System Actor is an actor for the FPG-EYE board written in Verilog. The actor require a hardware camera module to be mounted on the board.

System Actors camera structure

The actor Camera consists only of the file act_camera.v (in the directory svn-cal\hw\trunk\hdl_actors\actor_camera)

act_camera.v
The act_camera.v file consists of the state machine camera (written in Verilog) that manages the camera signals and the CAL protocol. The actor Camera has two CAL compatible output interfaces (sending tokens to other actors). The first CAL output has a data size of 8 bits and sends token containing the image pixel values, while the second CAL output, with a data size of 1 bit, sends a token whenever a new frame starts.

A simple example for camera actor is located in the svn-cal\hw\trunk\examples\example7 directory. All the three actors are used in this example: the LEDs act as a bar graph, whose length is proportional to the average image luminance.

example7: Board LEDs are turned on or off proportionally to the average image luminance

How to Interface a CAL Netlist to System Actors

To interface a CAL Netlist with an actor few steps are needed:

  • Create a Netlist in the CAL environment with the needed number of input and output ports
  • Build a wrapper in Verilog (or VHDL) that connects the netlist with the required system actors

How to Build a CAL Project with ispLEVER

First you must to have a Cal project with System Actors for FPG-EYE. See Create a Cal project with System Actors for instructions on how to do it. To build an ispLEVER CAL project we have to:

  • Open ispLEVER and click on new project.
    Click on "Open Project"
  • In the following window choose the project name and the its destination path. Please remember to select "Mixed Verilog/VHDL" for the option "Design Entry Type".
    Add "Name Project"
  • In the following window we have to select the device. For the FPG-EYE board we must use:
    • Family: LatticeXP2;
    • Device: LFXP2-17E;
    • Speed grade: 5;
    • Package type: PQFP208;
    • Operating conditions: Commercial;
    • PartName: LFXP2-17E-5QN208C.
      "Select Device"
  • Finally by clicking the End button
    "Add Source"
    the following window will be displayed:
    ispLEVER
  • To import lattice_cal.vhdl the library (svn-cal/hw/trunk/lib_vhdl) we have to right click on device and select "Import...".
    Import file
  • In the file window we can now select the file lattice_cal.vhdl
    Import the file "lattice_cal.vhdl"
  • Now by right clicking the lattice_cal.vhdl we can select "Library Name"
    Select "Library Name"
  • In the Box "VHDL Library Name" we can insert the namespace SystemBuilder
    Write: SystemBuilder
  • Each file created by the CAL compiler has an undefined module FD. This module is a D-FF (flip flop) declared in the xilinx library. This is part of a small reset synchronizer circuit. You have to remove this part because the Lattice software does not recognize it.
    There is a Perl script main_modify.pl that searches these FD instances in Verilog files and replaces them with a reset synchronizer. You can run this Perl script with the top level VHDL file as input. Before executing the Perl script, please check that all generated files are in the same folder. If the top level generated file name is main_nw.vhd, we can issue perl main_modify.pl main_nw.
    The script will produce a *_mod.v file for each parsed Verilog file.
  • After importing the files related to the various actors (LED, camera, and those related to our CAL netlist), a constraint file describing the connection between FPGA pins and logic blocks must be created. An example of these constraints can be found in "svn-cal\hw\trunk\examples\example7\isp_lever\example7.lpf"
  • We can finally compile the project, thus obtaining a binary JED file to program the FPG-EYE board.

How to Program the FPG-EYE board

See Programming the FPG-EYE board for instructions on how to download the JED file onto the board

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