Installation of Mico32/FPG-EYE development environment
This tutorial describes a set of steps needed to compile and deploy a platform on FPG-EYE board.
To achive this goal you need follow softwares from Lattice installed in your environment (follow links for download pages):
To download and use these softwares you need a Lattice registration and a fre license (follow instruction on Lattice web site)
Be careful: each version of ispLEVER need a correspondent version of LatticeMico System Development Tools, further 64 bit OSes are not supported by ispLEVER (even though we were able to install it on 64 bit Windows Vista/7, with some pain to be honest). In regard to ispVM System you need version 18.0 or superior. All FPG-EYE software development has been made with ispLEVER 8.0 and correspondant LatticeMico System Development Tools.
Hereunder it's supposed that all the tools are installed in the same base directory and we refer at this directory as: %ispTOOLS%
In addition to lattice software you need Evidence RT-Druid software (to run ERIKA Enterprise OS on Mico32 softcore) and a Python installation with pyserial module (to deploy your application on FPG-EYE external flash, with Evidence's boot loader Mico32 application).
Standard Mico32 components Patches
During FPG-EYE software development a few bugs in standard Mico32 components have been found and corrected. Especially we found small bugs in following components:
- SPI Flash Controller (Component directory: spi_flash. Verilog files: spi_flash_intf.v wb_intf.v)
- Async SRAM Controller (Componet directory: asram_top. Verilog files: asram_core.v)
We found these bugs in ispLEVER version 8.0 components. We don't know if they have been fixed in later versions.
You can find the patched verilog files here. To apply the patches you need to copy these new files in the right componets folders. The base directory for components is: %ispTOOLS%\micosystem\components. You have to put patched verilog files for each component in %ispTOOLS%\micosystem\components\<Component directory>\rtl\verilog to fix found bugs.