https://erika.tuxfamily.org/wiki/index.php?title=Special:Contributions&feed=atom&limit=50&target=ErikaddsErikaWiki - User contributions [en]2024-03-29T00:08:09ZFrom ErikaWikiMediaWiki 1.16.4https://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Installing_scicoslab_and_generating_code_from_a_Scicos_diagramTutorial: Installing scicoslab and generating code from a Scicos diagram2013-09-25T14:44:11Z<p>Erikadds: /* ScicosPack toolbox loader */</p>
<hr />
<div>This is the Wiki page dedicated to the Scicos code generator originally developed by Roberto Bucher from SUPSI Lugano.<br />
<br />
The code of the code generator is distributed under GPL2. The project is currently lead by Roberto Bucher, from SUPSI Lugano, and is hosted on the Evidence web site.<br />
<br />
<br />
<br />
= Scicoslab 4.4.1 and ScicosLab Pack 10.0: code generator for FLEX and EasyLab boards- Installation procedure =<br />
Steps to set up the Scicoslab code generation for FLEX and EasyLab boards<br />
# Download and install Cygwin from the [http://www.cygwin.com/ Cygwin site]. Here is a [http://download.tuxfamily.org/erika/webdownload/eeCygwin_1_7_9.zip minimal installation pack]. Cygwin is required to compile the code generated from your Scicos diagram.<br />
# Download Microsoft Visual C++ 2008 from the [http://www.microsoft.com/it-it/download/details.aspx?id=29 Microsoft Visual C++ site] ([http://www.microsoft.com/express/Downloads/#2008-Visual-CPP or use this link])and install it. It is required from the Evidence Scicoslab pack. <br />
# Download ScicosLab 4.4.1 from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab site] and install it. <br />
# Download Microchip MPLAB IDE from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en019469 MPLAB IDE site] and install it. It is required to program the dsPIC microcontroller mounted on the FLEX board or EasyLab board. Then download a C30 compiler, for example from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010065&part=SW006012 Microchip MPLAB C30 compiler site] and install it. A compiler is required to compile your control application. To program the dsPIC on the Flex board you need a programmer. You can buy a programmer for dsPIC from Microchip site. Programmers suggested are: Microchip MPLAB ICD2 or Microchip MPLAB ICD3. See Microchip for more informations:[http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010046 Microchip programmers site]. While for the EasyLab board the programmer is not required because it is equipped with one on board.<br />
# Download the latest Scicoslab pack from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab pack download page]. Unzip the pack and install it. To install the pack execute the installer.sce script file in ScicosLab (File -> Exec...). (If needed, run ScicosLab with administrator privileges). At the end of the installation restart ScicosLab for the changes to take effect.<br />
# Create and compile your first Scicos diagram (as shown here: [http://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communication An example of code-generation]), flash the microcontroller, test your application and ... enjoy! <br />
<br />
Please note, this version of the ScicosLab pack includes a stand-alone version of RT-Druid and a full version of Erika Enterprise.<br />
If you have any problem please contact us using the [http://erika.tuxfamily.org/forum/ Erika Forum]<br />
<br />
= Your first Scicos application =<br />
<br />
This Chapter will guide you to the creation, compilation and execution<br />
of a first simple Scicos example on a FLEX Demo board (or EasyLab board). The example<br />
created in this tutorial can be found in the directory<br />
<tt>scicos_ee/examples/scicos_flex/Led_sin</tt><br />
<tt>(scicos_ee/examples/scicos_easylab/Led_sin)</tt>.<br />
<br />
inside scicos pack base directory.<br />
<br />
If you are looking for a pre-built example, go directly to the next Section.<br />
<br />
== Creating the Scicos example files ==<br />
<br />
(Note the screenshow may refer to old versions of ScicosLab or Scilab 4.1.2).<br />
<br />
# Please start ScicosLab from the Start menu. The ScicosLab window appears.<br />
# Type <tt>scicos();</tt> as showed below in the Figure, and press Enter.<br />
#: [[File:scilab_splash.png|center|thumb|200px|The Scilab splash screen. Type <tt>scicos();</tt> to start Scicos.]]<br />
# The Scicos windows appears, as showed in Figure<br />
#: [[File:scicos_splash.png|center|thumb|200px|The Scicos splash screen.]]<br />
# You need to compile the Scicos blocks, if you didn't do it yet, in order to get the system working. To do that type these commands in ScicosLab window:<br />
#:cd ("%SCICOSLAB_HOME%\contrib\dspic"); // (%SCICOSLAB_HOME% means the installation path of ScicosLab...)<br />
#:exec ("builder.sce");<br />
#::'''IMPORTANT NOTE''': please check the correctness of this path. Newer Scicos Packs are installed under <tt>...\scicoslab-4.4.1\contrib\scicos_ee\scicos_flex\dspic</tt> <tt>(...\scicoslab-4.4.1\contrib\scicos_ee\scicos_easylab\dspic)</tt><br />
# Select ''Palettes'' from the ''Palette'' menu, as showed in Figure<br />
#: [[File:palette_menu.png|center|thumb|200px|The Palettes.]]<br />
# A little list appear in place of the menu. Select ''FLEX'' (''Easylab''), as showed in Figure<br />
#: [[File:palette_menu2.png|center|thumb|200px|The Palette list.]]<br />
# A windows appears, with some sink blocks specific for the FLEX boards (EasyLab board)<br />
#: [[File:palette.png|center|thumb|200px|The dsPIC Palette.]]<br />
# Single click on the FLEX-LED (EASYLAB-LED) block. The window selection moves to the Scicos window. The mouse now becomes a white rectangle of the dimension of the LED block. Single click somewhere in the white part of the window. A LED block is dropped in the diagram, like in Figure<br />
#: [[File:led.png|center|thumb|200px|The LED block is dropped in the design window.]]<br />
#* '''Note''': If you need to move a block, go over it with the mouse, press ''m'', then move the block and click on the new position!<br />
#* '''Note''': If you need to delete a block or a line, go over it with the mouse, then press ''d''!<br />
#* '''Note''': If some garbage appears on the diagram windos, don't panic! Just press ''r''!<br />
# Open the MCHP16-Sources palette, and repeat the same with the Sine block, placing it on the left of the LED block, as in Figure <br />
#: [[File:sineled.png|center|thumb|200px|Place the Sine block to the left of the LED block.]]<br />
# Link the black triangle of the Sine block to the black triangle of the LED block. To do that, press ''l'', then single click on the triangle of the Sine block (the ''source''), then click again on the triangle of the LED block (the ''sink''). See Figure<br />
#: [[File:link.png|center|thumb|200px|Sine and LED are now linked.]]<br />
# From the MCHP16-Sources Palette, which can be found il the palette list, choose the red clock, and put it on the diagram as shown in Figure<br />
#: [[File:clock.png|center|thumb|200px|Put the Clock block over the Sine and LED blocks.]]<br />
# Now connect the clock signal to the two blocks. To do that, single click on the red triangle of the <tt>clock</tt> block, then single click below it, then single click over the <tt>Sine</tt> block, then click on the red triangle of the <tt>Sine</tt> block. After that, single click on the line below the <tt>clock</tt> block, hit the key 'L' of keyboard, then over the <tt>LED</tt> block, then on the red triangle of the <tt>LED</tt> block. The result is shown in Figure<br />
#: [[File:redlink.png|center|thumb|200px|The Clock block is connected to the Sine and LED blocks.]]<br />
# Single click on the Clock block. Its properties window appears. Leave them untouched, and press OK. You can do the same on the Sine block. The two Figures below show these windows.<br />
#: [[File:clockproperties.png|center|thumb|200px|The Clock block properties.]]<br />
#: [[File:sineproperties.png|center|thumb|200px|The Sine block properties.]]<br />
# The code generator can produce code which only comes from a special block named ''Super Block''. For this reason, we need to create a Super Block enclosing the <tt>Sine</tt> and the <tt>LED</tt> blocks. To do that, select the ''Region to Super Block'' menu item from the ''Diagram'' menu (see Figure below).<br />
#: [[File:region2sb.png|center|thumb|200px|The Region to Super Block menu item.]]<br />
# Then, draw a selection which includes the <tt>Sine</tt>, the <tt>LED</tt>, and the red lines in a way that only ''one'' red line exits the selection, as shown in Figure<br />
#: [[File:sb.png|center|thumb|200px|The selection made to create a Super Block.]]<br />
# As a result, a Super Block is created (see Figure)<br />
#: [[File:sb1.png|center|thumb|200px|The Super Block.]]<br />
#: Which contains the Sine and LED blocks. To see these blocks, just single click on the Super Block, and another window will appear (see Figure). <br />
#: [[File:sb2.png|center|thumb|200px|The contents of the Super Block.]]<br />
# Please note that this window is very similar to the previous one except that the clock object is substituted by a placeholder signed with the number 1.<br />
#* '''Note''': The Diagram containing the Super Block is disabled when the Super Block diagram is displayed. Only one window can be enabled at a time in Scicos. The limitation will be removed in the next version of Scicos.<br />
# It is now time to save the two diagrams. From the ''File'' menu, choose ''Save as''. Save the diagram containing the Super Block as <tt>led_sin.cos</tt>.<br />
<br />
== Generating dsPIC code from a Scicos Diagram ==<br />
<br />
It is now time to generate the code for the example we just created.<br />
<br />
'''Note''': A copy of the file created in the previous steps is included inside the <tt>scicos_examples/led_sin</tt> directory. To open it, double click on the <tt>scicos_examples/led_sin/led_sin.cos</tt> file.<br />
<br />
# Select ''Set Target'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen0.png|center|thumb|200px|The CodeGen menu - Set target.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen3.png|center|thumb|200px|The SetTarget dialog box.]]<br />
# You can specify the target board (board_flex or board_easylab) using the second textbox. Please leave the other options unchanged.<br />
# Select ''FlexCodeGen'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen1.png|center|thumb|200px|The CodeGen menu - Flex code generator.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen2.png|center|thumb|200px|The FlexCodeGen dialog box.]]<br />
# You can specify the block name by modifying the <tt>New block's name</tt> textbox and the directory where all the files will be created by modifying the <tt>Created files Path</tt> textbox. <br />
#* '''IMPORTANT NOTE FOR WINDOWS USERS''': Choose a location where you have write permission. If you start 'ScicosLab' with administrator privileges there are no limitations in the choice of the destination folder.<br />
# Press ''Ok''. As a result, a set of files are generated in the output directory.<br />
# Then, Scicos automatically opens a console window, running in it the following commands:<br />
#* the RT-Druid template generator to instantiate the Scicos template application;<br />
#* the RT-Druid standalone code generator to produce the ERIKA Enterprise configuration files from the generated OIL file;<br />
#* the ''make'' application to compile the code.<br />
# The result of the code generation process is depicted in Figure \ref{fig:console}. <br />
#: [[File:console.png|center|thumb|200px|The compilation console.]]<br />
# The executable file is named <tt>pic30.cof</tt> (older versions of the Scicos-FLEX toolsed had it named <tt>pic30.elf</tt>) and it is located inside the <tt>Debug</tt> directory as usual for all the ERIKA Enterprise applications.<br />
# You can now program your application on your FLEX board. To do that, you need to open MPLABIDE as you usually do to program other ERIKA Enterprise applications. Please refer to the ERIKA Enterprise tutorial for dsPIC for more information.<br />
# Running the code on your FLEX board has the following behavior: the system led on the board flashes with a period of 20 seconds, and a duty cycle of around 6 seconds over 20. The explanation is the following: <br />
#* The system works like a synchronous control system, with a sampling frequency of 0.1 secs<br />
#* The ''Sine'' block output is a sinus with a frequency of 0.05, which correspond to a period of 20 s<br />
#* The LED block is directly linked to the system led, and is programmed to put on the system led when its input is greater than 0.5.<br />
#* Looking at the Figure below, it is clear that the sinus has a value greater than 0.5 for around a third of its period. Given that, the system led is on for around 6 seconds over 20.<br />
#: [[File:graphic.png|center|thumb|200px|A graphic of a Sine and of a constant value 0.5.]]<br />
<br />
= Internals of the genareted code =<br />
<br />
== Templates and customization of the generated application ==<br />
<br />
The default application wich is generated by the Scicos embedded code generator for dsPIC generates a basic application which uses ERIKA Enterprise with the FP kernel, a periodic task and an Alarm triggered by a timer interrupt to activate it.<br />
<br />
In general, it is likely that advanced users would like to customize the application which is generated by the code generator, to add other activities to be executed concurrently with the code generated from the Scicos design. Examples of this activities could be for example background activities for reporting, supervision, display, debug, and so on.<br />
<br />
Implementing such variations is very easy, because the application scheleton used by the code generator is contained inside a RT-Druid template. In particular, the default template is the <tt>pic30_empty_scicos</tt> template stored inside the <tt>examples/pic30/pic30_scicos</tt> directory under the dsPIC examples plugin in the Eclipse installation. The user can add a new template using the following steps:<br />
<br />
# Copy the <tt>examples/pic30/pic30_scicos</tt> directory in another location under the <tt>examples</tt> directory;<br />
# Change the <tt>ID</tt> of the template by modifying the <tt>template.xml</tt> file contained inside the directory. The <tt>ID</tt> is specified in the second line of the XML file as follows: <pre> <evidence_example version="1" ID="pic30_empty_scicos"></pre><br />
# Change the files included in the new template. If you need to add a new file, please remember to add it in the corresponding list in the <tt>template.xml</tt> file.<br />
<br />
Finally, specify the new template when generating the code in the Template textbox.<br />
<br />
== Assumptions of the default template ==<br />
The code generated by the Scilab/Scicos code generator for FLEX uses the template named <tt>pic30_empty_scicos</tt>, and has the following symplifing assumptions:<br />
<br />
# There is a single sampling time T_s in the system;<br />
# T_s is forced to 1 ms;<br />
# Every sampling time specified by the user under the Scicos design will be rounded to a multiple of a millisecond;<br />
# An ERIKA Enterprise counter is linked to the a periodic timer;<br />
# The periodic timer used in the dsPIC hardware is set to raise an interrupt every 1 ms;<br />
# An ERIKA Enterprise alarm is attached to the counter, to periodically activate a task;<br />
# The task body just calls the routines generated by the Scicos code generator. Which executes the functions you specified in the design;<br />
# The PWM object has a fixed period of 1 ms. This means that if the sampling period is a multiple of T_s, then the PWM will repeat the same duty cycle until the PWN value is changed;<br />
# The A/D converter always works ''on demand'', meaning it always executes the following steps:<br />
#* selects a channel;<br />
#* starts the conversion;<br />
#* waits for the end of the conversion (typically max 10 usec)<br />
#* it converts the result in a value from 0.0 V and 3.3 V<br />
<br />
== Installer Key Features ==<br />
The ScicosPack installer is a ScicosLab script executed by users to install/uninstall the ScicosPack.<br />
Key features:<br />
* automatic copy of files (please note, the user has to run ScicosLab with administrator privileges to install the toolbox)<br />
* automatic check of prerequisites <br />
* SMCube compiler configuration<br />
* License check<br />
* Microchip compiler support for Erika\RT-Druid project (certified OSEK micro-kernel)<br />
* automatic build of the ScicosPack sources<br />
* automatic creation of palettes<br />
* automatic loading of blocks-specific help pages<br />
* batch mode supported (for regression test with Jenkins)<br />
<br />
== External libraries linkage ==<br />
ScicosLab supports external DLL/SO linkage. This feature allows the user to link external C functions that are used to model new Scicos blocks for target-specific simulation and code generation.<br />
ScicosLab supports also DLL/SO creation in Windows and Linux hosts. <br />
To do this, ScicosLab automatically configure its environment by adding the required environment variables (MSVC variables in Windows).<br />
Type <tt>help ilib_for_link</tt> for further info (the function path is <tt>ScicosLab_441\macros\util\ilib_for_link.sci</tt>).<br />
External libraries linkage is done by the ScicoLab incremental linker by calling the function <tt>link</tt> (type <tt>help link</tt> for further info).<br />
As decribed in the <tt>link</tt> function's help page, the linkage needs also the C identifiers of the functions to be linked.<br />
Please note, if you create a DLL/SO library starting from an external C++ project (for example using Qt or MSVC++) the<br />
functions to be linked should have C names and not C++ names. This can be obtained using a construct like the following:<br />
At the top of the header file:<br />
<br />
<tt><br />
#ifdef __cplusplus<br />
extern "C" {<br />
#endif<br />
</tt><br />
<br />
At the bottom of the header file:<br />
<br />
<tt><br />
#ifdef __cplusplus<br />
}<br />
#endif<br />
</tt><br />
<br />
An example of a block's computational function for simulation is reported below:<br />
<br />
<tt><br />
__declspec(dllexport) void block_func(scicos_block *block, int flag) {<br />
if (flag == OutputUpdate){<br />
/* set output */<br />
block_in_out(block);<br />
}<br />
else if (flag == Ending){<br />
/* termination */ <br />
block_end(block);<br />
}<br />
else if (flag == Initialization){<br />
/* initialization */<br />
block_init(block);<br />
} <br />
}</tt><br />
<br />
For further info about the scicos-block structure look at:<br />
<tt>ScicosLab_441\routines\scicos\scicos_block4.h</tt><br />
<br />
== Code Generation ==<br />
The reference folder is the following:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen</tt><br />
The code-generation logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\FlexCodeGen_.sci</tt><br />
The target selection logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\SetTarget_.sci</tt><br />
Please note, the two logics save the code-generation user preferences in a specific field of the selected superblock.<br />
The superblocks provide to fields, named <tt>void2</tt> and <tt>void3</tt>, that can be used for generic purposes.<br />
New targets and new boards can be added by changing the function <tt>SetTarget_</tt>.<br />
Code generation for embedded application is implemented in the function <tt>FlexCodeGen_</tt>.<br />
Also the code-generation logic may require some minor change to support some specific feature of the new board,<br />
but normally changes are not required.<br />
Each block, designed for code generation, needs a computational target function in addition to the one used for simulation.<br />
The target function should have a prototype and a structure very similar to the computational function reported above.<br />
<br />
== How to add a new Scicos block ==<br />
The first step is to write the interfacing function (.sci) of the block.<br />
The interfacing function is a method that allows to define blocks settings, like the sizes and the types of the<br />
input/output ports of the block , internal states, feed-through properties as well as the internal parameters.<br />
The interfacing function defines also the graphics of the block and specifies the name of the block's <br />
computational function (the C function called in simulation).<br />
Then, the second step is to write the computational function and the target function as described above.<br />
Finally, the last step is to build\link the DLL\SO and to load in Scicos the interfacing function of the block <br />
(see commands like: "lib", "genlib", "exec", "getf", ...).<br />
Refer to this [http://erika.tuxfamily.org/wiki/index.php?title=How_to_add_a_new_Scicos_block_to_ERIKA_Enterprise tutorial] for further information.<br />
<br />
== ScicosPack toolbox loader ==<br />
The ScicosPack can be launched as an external toolbox starting form the ScicosLab menu. To do this, the ScicosPack folder<br />
should contain two scripts:<br />
* <tt>builder.sce</tt> (used to build the toolbox, not directly callable by the menu)<br />
* <tt>loader.sce</tt> (called to load the toolbox when it is choosed from the menu)<br />
<br />
== Regression test framework ==<br />
Each block is tested separately with a unit-test to verify no regression was introduced <br />
for both simulation and code-generation. This is done with a regression test framework (in batch-mode).<br />
Testcase SVN repository can be downloaded (read-only) from the following URL:<br />
<tt>svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/scilab_codegen/trunk/testcase</tt><br />
<br />
To launch testcase follow this procedure:<br />
* edit the script <tt>run_scicos_test.sh</tt> to change the environment variables SCIBASE, TESTBASE and ZIPBASE in accord with the directories used on your PC. (Please note you can also modify the script to avoid installation of the ScicosPack if already installed or the SVN checkout if the testcase folder has been already downloaded from the server.)<br />
* run the script to start tests execution<br />
<br />
== Linux support ==<br />
ScicosPack is also available on Linux hosts. <br />
ScicosPack for Linux will be committed and released as soon as possible.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.<br />
<br />
== Support for MSVC2010 and MSVC2012 (only for Windows) ==<br />
ScicosLab 4.4.1 supports Microsoft Visual C\C++ 2010. The presence of the MSVC2010 compiler is automatically recognized and the<br />
MSVC2010 environment is loaded during the ScicosLab initialization.<br />
MSVC2010 is requured by the ScicosPack because it has a number of DLLs builded with MSVC2010 to be linked in the launching step. <br />
ScicosLab doesn't support MSVC2012 directly. <br />
MSVC2012 can be supported writing a new version of the MSVC configuration functions.<br />
See <tt>ScicosLab_441\macros\util\configure_msvc.sci</tt> and similar for further informations.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Installing_scicoslab_and_generating_code_from_a_Scicos_diagramTutorial: Installing scicoslab and generating code from a Scicos diagram2013-09-25T14:43:17Z<p>Erikadds: /* Regression test framework */</p>
<hr />
<div>This is the Wiki page dedicated to the Scicos code generator originally developed by Roberto Bucher from SUPSI Lugano.<br />
<br />
The code of the code generator is distributed under GPL2. The project is currently lead by Roberto Bucher, from SUPSI Lugano, and is hosted on the Evidence web site.<br />
<br />
<br />
<br />
= Scicoslab 4.4.1 and ScicosLab Pack 10.0: code generator for FLEX and EasyLab boards- Installation procedure =<br />
Steps to set up the Scicoslab code generation for FLEX and EasyLab boards<br />
# Download and install Cygwin from the [http://www.cygwin.com/ Cygwin site]. Here is a [http://download.tuxfamily.org/erika/webdownload/eeCygwin_1_7_9.zip minimal installation pack]. Cygwin is required to compile the code generated from your Scicos diagram.<br />
# Download Microsoft Visual C++ 2008 from the [http://www.microsoft.com/it-it/download/details.aspx?id=29 Microsoft Visual C++ site] ([http://www.microsoft.com/express/Downloads/#2008-Visual-CPP or use this link])and install it. It is required from the Evidence Scicoslab pack. <br />
# Download ScicosLab 4.4.1 from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab site] and install it. <br />
# Download Microchip MPLAB IDE from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en019469 MPLAB IDE site] and install it. It is required to program the dsPIC microcontroller mounted on the FLEX board or EasyLab board. Then download a C30 compiler, for example from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010065&part=SW006012 Microchip MPLAB C30 compiler site] and install it. A compiler is required to compile your control application. To program the dsPIC on the Flex board you need a programmer. You can buy a programmer for dsPIC from Microchip site. Programmers suggested are: Microchip MPLAB ICD2 or Microchip MPLAB ICD3. See Microchip for more informations:[http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010046 Microchip programmers site]. While for the EasyLab board the programmer is not required because it is equipped with one on board.<br />
# Download the latest Scicoslab pack from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab pack download page]. Unzip the pack and install it. To install the pack execute the installer.sce script file in ScicosLab (File -> Exec...). (If needed, run ScicosLab with administrator privileges). At the end of the installation restart ScicosLab for the changes to take effect.<br />
# Create and compile your first Scicos diagram (as shown here: [http://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communication An example of code-generation]), flash the microcontroller, test your application and ... enjoy! <br />
<br />
Please note, this version of the ScicosLab pack includes a stand-alone version of RT-Druid and a full version of Erika Enterprise.<br />
If you have any problem please contact us using the [http://erika.tuxfamily.org/forum/ Erika Forum]<br />
<br />
= Your first Scicos application =<br />
<br />
This Chapter will guide you to the creation, compilation and execution<br />
of a first simple Scicos example on a FLEX Demo board (or EasyLab board). The example<br />
created in this tutorial can be found in the directory<br />
<tt>scicos_ee/examples/scicos_flex/Led_sin</tt><br />
<tt>(scicos_ee/examples/scicos_easylab/Led_sin)</tt>.<br />
<br />
inside scicos pack base directory.<br />
<br />
If you are looking for a pre-built example, go directly to the next Section.<br />
<br />
== Creating the Scicos example files ==<br />
<br />
(Note the screenshow may refer to old versions of ScicosLab or Scilab 4.1.2).<br />
<br />
# Please start ScicosLab from the Start menu. The ScicosLab window appears.<br />
# Type <tt>scicos();</tt> as showed below in the Figure, and press Enter.<br />
#: [[File:scilab_splash.png|center|thumb|200px|The Scilab splash screen. Type <tt>scicos();</tt> to start Scicos.]]<br />
# The Scicos windows appears, as showed in Figure<br />
#: [[File:scicos_splash.png|center|thumb|200px|The Scicos splash screen.]]<br />
# You need to compile the Scicos blocks, if you didn't do it yet, in order to get the system working. To do that type these commands in ScicosLab window:<br />
#:cd ("%SCICOSLAB_HOME%\contrib\dspic"); // (%SCICOSLAB_HOME% means the installation path of ScicosLab...)<br />
#:exec ("builder.sce");<br />
#::'''IMPORTANT NOTE''': please check the correctness of this path. Newer Scicos Packs are installed under <tt>...\scicoslab-4.4.1\contrib\scicos_ee\scicos_flex\dspic</tt> <tt>(...\scicoslab-4.4.1\contrib\scicos_ee\scicos_easylab\dspic)</tt><br />
# Select ''Palettes'' from the ''Palette'' menu, as showed in Figure<br />
#: [[File:palette_menu.png|center|thumb|200px|The Palettes.]]<br />
# A little list appear in place of the menu. Select ''FLEX'' (''Easylab''), as showed in Figure<br />
#: [[File:palette_menu2.png|center|thumb|200px|The Palette list.]]<br />
# A windows appears, with some sink blocks specific for the FLEX boards (EasyLab board)<br />
#: [[File:palette.png|center|thumb|200px|The dsPIC Palette.]]<br />
# Single click on the FLEX-LED (EASYLAB-LED) block. The window selection moves to the Scicos window. The mouse now becomes a white rectangle of the dimension of the LED block. Single click somewhere in the white part of the window. A LED block is dropped in the diagram, like in Figure<br />
#: [[File:led.png|center|thumb|200px|The LED block is dropped in the design window.]]<br />
#* '''Note''': If you need to move a block, go over it with the mouse, press ''m'', then move the block and click on the new position!<br />
#* '''Note''': If you need to delete a block or a line, go over it with the mouse, then press ''d''!<br />
#* '''Note''': If some garbage appears on the diagram windos, don't panic! Just press ''r''!<br />
# Open the MCHP16-Sources palette, and repeat the same with the Sine block, placing it on the left of the LED block, as in Figure <br />
#: [[File:sineled.png|center|thumb|200px|Place the Sine block to the left of the LED block.]]<br />
# Link the black triangle of the Sine block to the black triangle of the LED block. To do that, press ''l'', then single click on the triangle of the Sine block (the ''source''), then click again on the triangle of the LED block (the ''sink''). See Figure<br />
#: [[File:link.png|center|thumb|200px|Sine and LED are now linked.]]<br />
# From the MCHP16-Sources Palette, which can be found il the palette list, choose the red clock, and put it on the diagram as shown in Figure<br />
#: [[File:clock.png|center|thumb|200px|Put the Clock block over the Sine and LED blocks.]]<br />
# Now connect the clock signal to the two blocks. To do that, single click on the red triangle of the <tt>clock</tt> block, then single click below it, then single click over the <tt>Sine</tt> block, then click on the red triangle of the <tt>Sine</tt> block. After that, single click on the line below the <tt>clock</tt> block, hit the key 'L' of keyboard, then over the <tt>LED</tt> block, then on the red triangle of the <tt>LED</tt> block. The result is shown in Figure<br />
#: [[File:redlink.png|center|thumb|200px|The Clock block is connected to the Sine and LED blocks.]]<br />
# Single click on the Clock block. Its properties window appears. Leave them untouched, and press OK. You can do the same on the Sine block. The two Figures below show these windows.<br />
#: [[File:clockproperties.png|center|thumb|200px|The Clock block properties.]]<br />
#: [[File:sineproperties.png|center|thumb|200px|The Sine block properties.]]<br />
# The code generator can produce code which only comes from a special block named ''Super Block''. For this reason, we need to create a Super Block enclosing the <tt>Sine</tt> and the <tt>LED</tt> blocks. To do that, select the ''Region to Super Block'' menu item from the ''Diagram'' menu (see Figure below).<br />
#: [[File:region2sb.png|center|thumb|200px|The Region to Super Block menu item.]]<br />
# Then, draw a selection which includes the <tt>Sine</tt>, the <tt>LED</tt>, and the red lines in a way that only ''one'' red line exits the selection, as shown in Figure<br />
#: [[File:sb.png|center|thumb|200px|The selection made to create a Super Block.]]<br />
# As a result, a Super Block is created (see Figure)<br />
#: [[File:sb1.png|center|thumb|200px|The Super Block.]]<br />
#: Which contains the Sine and LED blocks. To see these blocks, just single click on the Super Block, and another window will appear (see Figure). <br />
#: [[File:sb2.png|center|thumb|200px|The contents of the Super Block.]]<br />
# Please note that this window is very similar to the previous one except that the clock object is substituted by a placeholder signed with the number 1.<br />
#* '''Note''': The Diagram containing the Super Block is disabled when the Super Block diagram is displayed. Only one window can be enabled at a time in Scicos. The limitation will be removed in the next version of Scicos.<br />
# It is now time to save the two diagrams. From the ''File'' menu, choose ''Save as''. Save the diagram containing the Super Block as <tt>led_sin.cos</tt>.<br />
<br />
== Generating dsPIC code from a Scicos Diagram ==<br />
<br />
It is now time to generate the code for the example we just created.<br />
<br />
'''Note''': A copy of the file created in the previous steps is included inside the <tt>scicos_examples/led_sin</tt> directory. To open it, double click on the <tt>scicos_examples/led_sin/led_sin.cos</tt> file.<br />
<br />
# Select ''Set Target'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen0.png|center|thumb|200px|The CodeGen menu - Set target.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen3.png|center|thumb|200px|The SetTarget dialog box.]]<br />
# You can specify the target board (board_flex or board_easylab) using the second textbox. Please leave the other options unchanged.<br />
# Select ''FlexCodeGen'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen1.png|center|thumb|200px|The CodeGen menu - Flex code generator.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen2.png|center|thumb|200px|The FlexCodeGen dialog box.]]<br />
# You can specify the block name by modifying the <tt>New block's name</tt> textbox and the directory where all the files will be created by modifying the <tt>Created files Path</tt> textbox. <br />
#* '''IMPORTANT NOTE FOR WINDOWS USERS''': Choose a location where you have write permission. If you start 'ScicosLab' with administrator privileges there are no limitations in the choice of the destination folder.<br />
# Press ''Ok''. As a result, a set of files are generated in the output directory.<br />
# Then, Scicos automatically opens a console window, running in it the following commands:<br />
#* the RT-Druid template generator to instantiate the Scicos template application;<br />
#* the RT-Druid standalone code generator to produce the ERIKA Enterprise configuration files from the generated OIL file;<br />
#* the ''make'' application to compile the code.<br />
# The result of the code generation process is depicted in Figure \ref{fig:console}. <br />
#: [[File:console.png|center|thumb|200px|The compilation console.]]<br />
# The executable file is named <tt>pic30.cof</tt> (older versions of the Scicos-FLEX toolsed had it named <tt>pic30.elf</tt>) and it is located inside the <tt>Debug</tt> directory as usual for all the ERIKA Enterprise applications.<br />
# You can now program your application on your FLEX board. To do that, you need to open MPLABIDE as you usually do to program other ERIKA Enterprise applications. Please refer to the ERIKA Enterprise tutorial for dsPIC for more information.<br />
# Running the code on your FLEX board has the following behavior: the system led on the board flashes with a period of 20 seconds, and a duty cycle of around 6 seconds over 20. The explanation is the following: <br />
#* The system works like a synchronous control system, with a sampling frequency of 0.1 secs<br />
#* The ''Sine'' block output is a sinus with a frequency of 0.05, which correspond to a period of 20 s<br />
#* The LED block is directly linked to the system led, and is programmed to put on the system led when its input is greater than 0.5.<br />
#* Looking at the Figure below, it is clear that the sinus has a value greater than 0.5 for around a third of its period. Given that, the system led is on for around 6 seconds over 20.<br />
#: [[File:graphic.png|center|thumb|200px|A graphic of a Sine and of a constant value 0.5.]]<br />
<br />
= Internals of the genareted code =<br />
<br />
== Templates and customization of the generated application ==<br />
<br />
The default application wich is generated by the Scicos embedded code generator for dsPIC generates a basic application which uses ERIKA Enterprise with the FP kernel, a periodic task and an Alarm triggered by a timer interrupt to activate it.<br />
<br />
In general, it is likely that advanced users would like to customize the application which is generated by the code generator, to add other activities to be executed concurrently with the code generated from the Scicos design. Examples of this activities could be for example background activities for reporting, supervision, display, debug, and so on.<br />
<br />
Implementing such variations is very easy, because the application scheleton used by the code generator is contained inside a RT-Druid template. In particular, the default template is the <tt>pic30_empty_scicos</tt> template stored inside the <tt>examples/pic30/pic30_scicos</tt> directory under the dsPIC examples plugin in the Eclipse installation. The user can add a new template using the following steps:<br />
<br />
# Copy the <tt>examples/pic30/pic30_scicos</tt> directory in another location under the <tt>examples</tt> directory;<br />
# Change the <tt>ID</tt> of the template by modifying the <tt>template.xml</tt> file contained inside the directory. The <tt>ID</tt> is specified in the second line of the XML file as follows: <pre> <evidence_example version="1" ID="pic30_empty_scicos"></pre><br />
# Change the files included in the new template. If you need to add a new file, please remember to add it in the corresponding list in the <tt>template.xml</tt> file.<br />
<br />
Finally, specify the new template when generating the code in the Template textbox.<br />
<br />
== Assumptions of the default template ==<br />
The code generated by the Scilab/Scicos code generator for FLEX uses the template named <tt>pic30_empty_scicos</tt>, and has the following symplifing assumptions:<br />
<br />
# There is a single sampling time T_s in the system;<br />
# T_s is forced to 1 ms;<br />
# Every sampling time specified by the user under the Scicos design will be rounded to a multiple of a millisecond;<br />
# An ERIKA Enterprise counter is linked to the a periodic timer;<br />
# The periodic timer used in the dsPIC hardware is set to raise an interrupt every 1 ms;<br />
# An ERIKA Enterprise alarm is attached to the counter, to periodically activate a task;<br />
# The task body just calls the routines generated by the Scicos code generator. Which executes the functions you specified in the design;<br />
# The PWM object has a fixed period of 1 ms. This means that if the sampling period is a multiple of T_s, then the PWM will repeat the same duty cycle until the PWN value is changed;<br />
# The A/D converter always works ''on demand'', meaning it always executes the following steps:<br />
#* selects a channel;<br />
#* starts the conversion;<br />
#* waits for the end of the conversion (typically max 10 usec)<br />
#* it converts the result in a value from 0.0 V and 3.3 V<br />
<br />
== Installer Key Features ==<br />
The ScicosPack installer is a ScicosLab script executed by users to install/uninstall the ScicosPack.<br />
Key features:<br />
* automatic copy of files (please note, the user has to run ScicosLab with administrator privileges to install the toolbox)<br />
* automatic check of prerequisites <br />
* SMCube compiler configuration<br />
* License check<br />
* Microchip compiler support for Erika\RT-Druid project (certified OSEK micro-kernel)<br />
* automatic build of the ScicosPack sources<br />
* automatic creation of palettes<br />
* automatic loading of blocks-specific help pages<br />
* batch mode supported (for regression test with Jenkins)<br />
<br />
== External libraries linkage ==<br />
ScicosLab supports external DLL/SO linkage. This feature allows the user to link external C functions that are used to model new Scicos blocks for target-specific simulation and code generation.<br />
ScicosLab supports also DLL/SO creation in Windows and Linux hosts. <br />
To do this, ScicosLab automatically configure its environment by adding the required environment variables (MSVC variables in Windows).<br />
Type <tt>help ilib_for_link</tt> for further info (the function path is <tt>ScicosLab_441\macros\util\ilib_for_link.sci</tt>).<br />
External libraries linkage is done by the ScicoLab incremental linker by calling the function <tt>link</tt> (type <tt>help link</tt> for further info).<br />
As decribed in the <tt>link</tt> function's help page, the linkage needs also the C identifiers of the functions to be linked.<br />
Please note, if you create a DLL/SO library starting from an external C++ project (for example using Qt or MSVC++) the<br />
functions to be linked should have C names and not C++ names. This can be obtained using a construct like the following:<br />
At the top of the header file:<br />
<br />
<tt><br />
#ifdef __cplusplus<br />
extern "C" {<br />
#endif<br />
</tt><br />
<br />
At the bottom of the header file:<br />
<br />
<tt><br />
#ifdef __cplusplus<br />
}<br />
#endif<br />
</tt><br />
<br />
An example of a block's computational function for simulation is reported below:<br />
<br />
<tt><br />
__declspec(dllexport) void block_func(scicos_block *block, int flag) {<br />
if (flag == OutputUpdate){<br />
/* set output */<br />
block_in_out(block);<br />
}<br />
else if (flag == Ending){<br />
/* termination */ <br />
block_end(block);<br />
}<br />
else if (flag == Initialization){<br />
/* initialization */<br />
block_init(block);<br />
} <br />
}</tt><br />
<br />
For further info about the scicos-block structure look at:<br />
<tt>ScicosLab_441\routines\scicos\scicos_block4.h</tt><br />
<br />
== Code Generation ==<br />
The reference folder is the following:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen</tt><br />
The code-generation logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\FlexCodeGen_.sci</tt><br />
The target selection logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\SetTarget_.sci</tt><br />
Please note, the two logics save the code-generation user preferences in a specific field of the selected superblock.<br />
The superblocks provide to fields, named <tt>void2</tt> and <tt>void3</tt>, that can be used for generic purposes.<br />
New targets and new boards can be added by changing the function <tt>SetTarget_</tt>.<br />
Code generation for embedded application is implemented in the function <tt>FlexCodeGen_</tt>.<br />
Also the code-generation logic may require some minor change to support some specific feature of the new board,<br />
but normally changes are not required.<br />
Each block, designed for code generation, needs a computational target function in addition to the one used for simulation.<br />
The target function should have a prototype and a structure very similar to the computational function reported above.<br />
<br />
== How to add a new Scicos block ==<br />
The first step is to write the interfacing function (.sci) of the block.<br />
The interfacing function is a method that allows to define blocks settings, like the sizes and the types of the<br />
input/output ports of the block , internal states, feed-through properties as well as the internal parameters.<br />
The interfacing function defines also the graphics of the block and specifies the name of the block's <br />
computational function (the C function called in simulation).<br />
Then, the second step is to write the computational function and the target function as described above.<br />
Finally, the last step is to build\link the DLL\SO and to load in Scicos the interfacing function of the block <br />
(see commands like: "lib", "genlib", "exec", "getf", ...).<br />
Refer to this [http://erika.tuxfamily.org/wiki/index.php?title=How_to_add_a_new_Scicos_block_to_ERIKA_Enterprise tutorial] for further information.<br />
<br />
== ScicosPack toolbox loader ==<br />
The ScicosPack can be launched as an external toolbox starting form the ScicosLab menu. To do this, the ScicosPack folder<br />
should contain two scripts:<br />
- <tt>builder.sce</tt> (used to build the toolbox, not directly callable by the menu)<br />
- <tt>loader.sce</tt> (called to load the toolbox when it is choosed from the menu)<br />
<br />
== Regression test framework ==<br />
Each block is tested separately with a unit-test to verify no regression was introduced <br />
for both simulation and code-generation. This is done with a regression test framework (in batch-mode).<br />
Testcase SVN repository can be downloaded (read-only) from the following URL:<br />
<tt>svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/scilab_codegen/trunk/testcase</tt><br />
<br />
To launch testcase follow this procedure:<br />
* edit the script <tt>run_scicos_test.sh</tt> to change the environment variables SCIBASE, TESTBASE and ZIPBASE in accord with the directories used on your PC. (Please note you can also modify the script to avoid installation of the ScicosPack if already installed or the SVN checkout if the testcase folder has been already downloaded from the server.)<br />
* run the script to start tests execution<br />
<br />
== Linux support ==<br />
ScicosPack is also available on Linux hosts. <br />
ScicosPack for Linux will be committed and released as soon as possible.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.<br />
<br />
== Support for MSVC2010 and MSVC2012 (only for Windows) ==<br />
ScicosLab 4.4.1 supports Microsoft Visual C\C++ 2010. The presence of the MSVC2010 compiler is automatically recognized and the<br />
MSVC2010 environment is loaded during the ScicosLab initialization.<br />
MSVC2010 is requured by the ScicosPack because it has a number of DLLs builded with MSVC2010 to be linked in the launching step. <br />
ScicosLab doesn't support MSVC2012 directly. <br />
MSVC2012 can be supported writing a new version of the MSVC configuration functions.<br />
See <tt>ScicosLab_441\macros\util\configure_msvc.sci</tt> and similar for further informations.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Installing_scicoslab_and_generating_code_from_a_Scicos_diagramTutorial: Installing scicoslab and generating code from a Scicos diagram2013-09-25T14:41:23Z<p>Erikadds: /* External libraries linkage */</p>
<hr />
<div>This is the Wiki page dedicated to the Scicos code generator originally developed by Roberto Bucher from SUPSI Lugano.<br />
<br />
The code of the code generator is distributed under GPL2. The project is currently lead by Roberto Bucher, from SUPSI Lugano, and is hosted on the Evidence web site.<br />
<br />
<br />
<br />
= Scicoslab 4.4.1 and ScicosLab Pack 10.0: code generator for FLEX and EasyLab boards- Installation procedure =<br />
Steps to set up the Scicoslab code generation for FLEX and EasyLab boards<br />
# Download and install Cygwin from the [http://www.cygwin.com/ Cygwin site]. Here is a [http://download.tuxfamily.org/erika/webdownload/eeCygwin_1_7_9.zip minimal installation pack]. Cygwin is required to compile the code generated from your Scicos diagram.<br />
# Download Microsoft Visual C++ 2008 from the [http://www.microsoft.com/it-it/download/details.aspx?id=29 Microsoft Visual C++ site] ([http://www.microsoft.com/express/Downloads/#2008-Visual-CPP or use this link])and install it. It is required from the Evidence Scicoslab pack. <br />
# Download ScicosLab 4.4.1 from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab site] and install it. <br />
# Download Microchip MPLAB IDE from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en019469 MPLAB IDE site] and install it. It is required to program the dsPIC microcontroller mounted on the FLEX board or EasyLab board. Then download a C30 compiler, for example from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010065&part=SW006012 Microchip MPLAB C30 compiler site] and install it. A compiler is required to compile your control application. To program the dsPIC on the Flex board you need a programmer. You can buy a programmer for dsPIC from Microchip site. Programmers suggested are: Microchip MPLAB ICD2 or Microchip MPLAB ICD3. See Microchip for more informations:[http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010046 Microchip programmers site]. While for the EasyLab board the programmer is not required because it is equipped with one on board.<br />
# Download the latest Scicoslab pack from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab pack download page]. Unzip the pack and install it. To install the pack execute the installer.sce script file in ScicosLab (File -> Exec...). (If needed, run ScicosLab with administrator privileges). At the end of the installation restart ScicosLab for the changes to take effect.<br />
# Create and compile your first Scicos diagram (as shown here: [http://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communication An example of code-generation]), flash the microcontroller, test your application and ... enjoy! <br />
<br />
Please note, this version of the ScicosLab pack includes a stand-alone version of RT-Druid and a full version of Erika Enterprise.<br />
If you have any problem please contact us using the [http://erika.tuxfamily.org/forum/ Erika Forum]<br />
<br />
= Your first Scicos application =<br />
<br />
This Chapter will guide you to the creation, compilation and execution<br />
of a first simple Scicos example on a FLEX Demo board (or EasyLab board). The example<br />
created in this tutorial can be found in the directory<br />
<tt>scicos_ee/examples/scicos_flex/Led_sin</tt><br />
<tt>(scicos_ee/examples/scicos_easylab/Led_sin)</tt>.<br />
<br />
inside scicos pack base directory.<br />
<br />
If you are looking for a pre-built example, go directly to the next Section.<br />
<br />
== Creating the Scicos example files ==<br />
<br />
(Note the screenshow may refer to old versions of ScicosLab or Scilab 4.1.2).<br />
<br />
# Please start ScicosLab from the Start menu. The ScicosLab window appears.<br />
# Type <tt>scicos();</tt> as showed below in the Figure, and press Enter.<br />
#: [[File:scilab_splash.png|center|thumb|200px|The Scilab splash screen. Type <tt>scicos();</tt> to start Scicos.]]<br />
# The Scicos windows appears, as showed in Figure<br />
#: [[File:scicos_splash.png|center|thumb|200px|The Scicos splash screen.]]<br />
# You need to compile the Scicos blocks, if you didn't do it yet, in order to get the system working. To do that type these commands in ScicosLab window:<br />
#:cd ("%SCICOSLAB_HOME%\contrib\dspic"); // (%SCICOSLAB_HOME% means the installation path of ScicosLab...)<br />
#:exec ("builder.sce");<br />
#::'''IMPORTANT NOTE''': please check the correctness of this path. Newer Scicos Packs are installed under <tt>...\scicoslab-4.4.1\contrib\scicos_ee\scicos_flex\dspic</tt> <tt>(...\scicoslab-4.4.1\contrib\scicos_ee\scicos_easylab\dspic)</tt><br />
# Select ''Palettes'' from the ''Palette'' menu, as showed in Figure<br />
#: [[File:palette_menu.png|center|thumb|200px|The Palettes.]]<br />
# A little list appear in place of the menu. Select ''FLEX'' (''Easylab''), as showed in Figure<br />
#: [[File:palette_menu2.png|center|thumb|200px|The Palette list.]]<br />
# A windows appears, with some sink blocks specific for the FLEX boards (EasyLab board)<br />
#: [[File:palette.png|center|thumb|200px|The dsPIC Palette.]]<br />
# Single click on the FLEX-LED (EASYLAB-LED) block. The window selection moves to the Scicos window. The mouse now becomes a white rectangle of the dimension of the LED block. Single click somewhere in the white part of the window. A LED block is dropped in the diagram, like in Figure<br />
#: [[File:led.png|center|thumb|200px|The LED block is dropped in the design window.]]<br />
#* '''Note''': If you need to move a block, go over it with the mouse, press ''m'', then move the block and click on the new position!<br />
#* '''Note''': If you need to delete a block or a line, go over it with the mouse, then press ''d''!<br />
#* '''Note''': If some garbage appears on the diagram windos, don't panic! Just press ''r''!<br />
# Open the MCHP16-Sources palette, and repeat the same with the Sine block, placing it on the left of the LED block, as in Figure <br />
#: [[File:sineled.png|center|thumb|200px|Place the Sine block to the left of the LED block.]]<br />
# Link the black triangle of the Sine block to the black triangle of the LED block. To do that, press ''l'', then single click on the triangle of the Sine block (the ''source''), then click again on the triangle of the LED block (the ''sink''). See Figure<br />
#: [[File:link.png|center|thumb|200px|Sine and LED are now linked.]]<br />
# From the MCHP16-Sources Palette, which can be found il the palette list, choose the red clock, and put it on the diagram as shown in Figure<br />
#: [[File:clock.png|center|thumb|200px|Put the Clock block over the Sine and LED blocks.]]<br />
# Now connect the clock signal to the two blocks. To do that, single click on the red triangle of the <tt>clock</tt> block, then single click below it, then single click over the <tt>Sine</tt> block, then click on the red triangle of the <tt>Sine</tt> block. After that, single click on the line below the <tt>clock</tt> block, hit the key 'L' of keyboard, then over the <tt>LED</tt> block, then on the red triangle of the <tt>LED</tt> block. The result is shown in Figure<br />
#: [[File:redlink.png|center|thumb|200px|The Clock block is connected to the Sine and LED blocks.]]<br />
# Single click on the Clock block. Its properties window appears. Leave them untouched, and press OK. You can do the same on the Sine block. The two Figures below show these windows.<br />
#: [[File:clockproperties.png|center|thumb|200px|The Clock block properties.]]<br />
#: [[File:sineproperties.png|center|thumb|200px|The Sine block properties.]]<br />
# The code generator can produce code which only comes from a special block named ''Super Block''. For this reason, we need to create a Super Block enclosing the <tt>Sine</tt> and the <tt>LED</tt> blocks. To do that, select the ''Region to Super Block'' menu item from the ''Diagram'' menu (see Figure below).<br />
#: [[File:region2sb.png|center|thumb|200px|The Region to Super Block menu item.]]<br />
# Then, draw a selection which includes the <tt>Sine</tt>, the <tt>LED</tt>, and the red lines in a way that only ''one'' red line exits the selection, as shown in Figure<br />
#: [[File:sb.png|center|thumb|200px|The selection made to create a Super Block.]]<br />
# As a result, a Super Block is created (see Figure)<br />
#: [[File:sb1.png|center|thumb|200px|The Super Block.]]<br />
#: Which contains the Sine and LED blocks. To see these blocks, just single click on the Super Block, and another window will appear (see Figure). <br />
#: [[File:sb2.png|center|thumb|200px|The contents of the Super Block.]]<br />
# Please note that this window is very similar to the previous one except that the clock object is substituted by a placeholder signed with the number 1.<br />
#* '''Note''': The Diagram containing the Super Block is disabled when the Super Block diagram is displayed. Only one window can be enabled at a time in Scicos. The limitation will be removed in the next version of Scicos.<br />
# It is now time to save the two diagrams. From the ''File'' menu, choose ''Save as''. Save the diagram containing the Super Block as <tt>led_sin.cos</tt>.<br />
<br />
== Generating dsPIC code from a Scicos Diagram ==<br />
<br />
It is now time to generate the code for the example we just created.<br />
<br />
'''Note''': A copy of the file created in the previous steps is included inside the <tt>scicos_examples/led_sin</tt> directory. To open it, double click on the <tt>scicos_examples/led_sin/led_sin.cos</tt> file.<br />
<br />
# Select ''Set Target'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen0.png|center|thumb|200px|The CodeGen menu - Set target.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen3.png|center|thumb|200px|The SetTarget dialog box.]]<br />
# You can specify the target board (board_flex or board_easylab) using the second textbox. Please leave the other options unchanged.<br />
# Select ''FlexCodeGen'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen1.png|center|thumb|200px|The CodeGen menu - Flex code generator.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen2.png|center|thumb|200px|The FlexCodeGen dialog box.]]<br />
# You can specify the block name by modifying the <tt>New block's name</tt> textbox and the directory where all the files will be created by modifying the <tt>Created files Path</tt> textbox. <br />
#* '''IMPORTANT NOTE FOR WINDOWS USERS''': Choose a location where you have write permission. If you start 'ScicosLab' with administrator privileges there are no limitations in the choice of the destination folder.<br />
# Press ''Ok''. As a result, a set of files are generated in the output directory.<br />
# Then, Scicos automatically opens a console window, running in it the following commands:<br />
#* the RT-Druid template generator to instantiate the Scicos template application;<br />
#* the RT-Druid standalone code generator to produce the ERIKA Enterprise configuration files from the generated OIL file;<br />
#* the ''make'' application to compile the code.<br />
# The result of the code generation process is depicted in Figure \ref{fig:console}. <br />
#: [[File:console.png|center|thumb|200px|The compilation console.]]<br />
# The executable file is named <tt>pic30.cof</tt> (older versions of the Scicos-FLEX toolsed had it named <tt>pic30.elf</tt>) and it is located inside the <tt>Debug</tt> directory as usual for all the ERIKA Enterprise applications.<br />
# You can now program your application on your FLEX board. To do that, you need to open MPLABIDE as you usually do to program other ERIKA Enterprise applications. Please refer to the ERIKA Enterprise tutorial for dsPIC for more information.<br />
# Running the code on your FLEX board has the following behavior: the system led on the board flashes with a period of 20 seconds, and a duty cycle of around 6 seconds over 20. The explanation is the following: <br />
#* The system works like a synchronous control system, with a sampling frequency of 0.1 secs<br />
#* The ''Sine'' block output is a sinus with a frequency of 0.05, which correspond to a period of 20 s<br />
#* The LED block is directly linked to the system led, and is programmed to put on the system led when its input is greater than 0.5.<br />
#* Looking at the Figure below, it is clear that the sinus has a value greater than 0.5 for around a third of its period. Given that, the system led is on for around 6 seconds over 20.<br />
#: [[File:graphic.png|center|thumb|200px|A graphic of a Sine and of a constant value 0.5.]]<br />
<br />
= Internals of the genareted code =<br />
<br />
== Templates and customization of the generated application ==<br />
<br />
The default application wich is generated by the Scicos embedded code generator for dsPIC generates a basic application which uses ERIKA Enterprise with the FP kernel, a periodic task and an Alarm triggered by a timer interrupt to activate it.<br />
<br />
In general, it is likely that advanced users would like to customize the application which is generated by the code generator, to add other activities to be executed concurrently with the code generated from the Scicos design. Examples of this activities could be for example background activities for reporting, supervision, display, debug, and so on.<br />
<br />
Implementing such variations is very easy, because the application scheleton used by the code generator is contained inside a RT-Druid template. In particular, the default template is the <tt>pic30_empty_scicos</tt> template stored inside the <tt>examples/pic30/pic30_scicos</tt> directory under the dsPIC examples plugin in the Eclipse installation. The user can add a new template using the following steps:<br />
<br />
# Copy the <tt>examples/pic30/pic30_scicos</tt> directory in another location under the <tt>examples</tt> directory;<br />
# Change the <tt>ID</tt> of the template by modifying the <tt>template.xml</tt> file contained inside the directory. The <tt>ID</tt> is specified in the second line of the XML file as follows: <pre> <evidence_example version="1" ID="pic30_empty_scicos"></pre><br />
# Change the files included in the new template. If you need to add a new file, please remember to add it in the corresponding list in the <tt>template.xml</tt> file.<br />
<br />
Finally, specify the new template when generating the code in the Template textbox.<br />
<br />
== Assumptions of the default template ==<br />
The code generated by the Scilab/Scicos code generator for FLEX uses the template named <tt>pic30_empty_scicos</tt>, and has the following symplifing assumptions:<br />
<br />
# There is a single sampling time T_s in the system;<br />
# T_s is forced to 1 ms;<br />
# Every sampling time specified by the user under the Scicos design will be rounded to a multiple of a millisecond;<br />
# An ERIKA Enterprise counter is linked to the a periodic timer;<br />
# The periodic timer used in the dsPIC hardware is set to raise an interrupt every 1 ms;<br />
# An ERIKA Enterprise alarm is attached to the counter, to periodically activate a task;<br />
# The task body just calls the routines generated by the Scicos code generator. Which executes the functions you specified in the design;<br />
# The PWM object has a fixed period of 1 ms. This means that if the sampling period is a multiple of T_s, then the PWM will repeat the same duty cycle until the PWN value is changed;<br />
# The A/D converter always works ''on demand'', meaning it always executes the following steps:<br />
#* selects a channel;<br />
#* starts the conversion;<br />
#* waits for the end of the conversion (typically max 10 usec)<br />
#* it converts the result in a value from 0.0 V and 3.3 V<br />
<br />
== Installer Key Features ==<br />
The ScicosPack installer is a ScicosLab script executed by users to install/uninstall the ScicosPack.<br />
Key features:<br />
* automatic copy of files (please note, the user has to run ScicosLab with administrator privileges to install the toolbox)<br />
* automatic check of prerequisites <br />
* SMCube compiler configuration<br />
* License check<br />
* Microchip compiler support for Erika\RT-Druid project (certified OSEK micro-kernel)<br />
* automatic build of the ScicosPack sources<br />
* automatic creation of palettes<br />
* automatic loading of blocks-specific help pages<br />
* batch mode supported (for regression test with Jenkins)<br />
<br />
== External libraries linkage ==<br />
ScicosLab supports external DLL/SO linkage. This feature allows the user to link external C functions that are used to model new Scicos blocks for target-specific simulation and code generation.<br />
ScicosLab supports also DLL/SO creation in Windows and Linux hosts. <br />
To do this, ScicosLab automatically configure its environment by adding the required environment variables (MSVC variables in Windows).<br />
Type <tt>help ilib_for_link</tt> for further info (the function path is <tt>ScicosLab_441\macros\util\ilib_for_link.sci</tt>).<br />
External libraries linkage is done by the ScicoLab incremental linker by calling the function <tt>link</tt> (type <tt>help link</tt> for further info).<br />
As decribed in the <tt>link</tt> function's help page, the linkage needs also the C identifiers of the functions to be linked.<br />
Please note, if you create a DLL/SO library starting from an external C++ project (for example using Qt or MSVC++) the<br />
functions to be linked should have C names and not C++ names. This can be obtained using a construct like the following:<br />
At the top of the header file:<br />
<br />
<tt><br />
#ifdef __cplusplus<br />
extern "C" {<br />
#endif<br />
</tt><br />
<br />
At the bottom of the header file:<br />
<br />
<tt><br />
#ifdef __cplusplus<br />
}<br />
#endif<br />
</tt><br />
<br />
An example of a block's computational function for simulation is reported below:<br />
<br />
<tt><br />
__declspec(dllexport) void block_func(scicos_block *block, int flag) {<br />
if (flag == OutputUpdate){<br />
/* set output */<br />
block_in_out(block);<br />
}<br />
else if (flag == Ending){<br />
/* termination */ <br />
block_end(block);<br />
}<br />
else if (flag == Initialization){<br />
/* initialization */<br />
block_init(block);<br />
} <br />
}</tt><br />
<br />
For further info about the scicos-block structure look at:<br />
<tt>ScicosLab_441\routines\scicos\scicos_block4.h</tt><br />
<br />
== Code Generation ==<br />
The reference folder is the following:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen</tt><br />
The code-generation logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\FlexCodeGen_.sci</tt><br />
The target selection logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\SetTarget_.sci</tt><br />
Please note, the two logics save the code-generation user preferences in a specific field of the selected superblock.<br />
The superblocks provide to fields, named <tt>void2</tt> and <tt>void3</tt>, that can be used for generic purposes.<br />
New targets and new boards can be added by changing the function <tt>SetTarget_</tt>.<br />
Code generation for embedded application is implemented in the function <tt>FlexCodeGen_</tt>.<br />
Also the code-generation logic may require some minor change to support some specific feature of the new board,<br />
but normally changes are not required.<br />
Each block, designed for code generation, needs a computational target function in addition to the one used for simulation.<br />
The target function should have a prototype and a structure very similar to the computational function reported above.<br />
<br />
== How to add a new Scicos block ==<br />
The first step is to write the interfacing function (.sci) of the block.<br />
The interfacing function is a method that allows to define blocks settings, like the sizes and the types of the<br />
input/output ports of the block , internal states, feed-through properties as well as the internal parameters.<br />
The interfacing function defines also the graphics of the block and specifies the name of the block's <br />
computational function (the C function called in simulation).<br />
Then, the second step is to write the computational function and the target function as described above.<br />
Finally, the last step is to build\link the DLL\SO and to load in Scicos the interfacing function of the block <br />
(see commands like: "lib", "genlib", "exec", "getf", ...).<br />
Refer to this [http://erika.tuxfamily.org/wiki/index.php?title=How_to_add_a_new_Scicos_block_to_ERIKA_Enterprise tutorial] for further information.<br />
<br />
== ScicosPack toolbox loader ==<br />
The ScicosPack can be launched as an external toolbox starting form the ScicosLab menu. To do this, the ScicosPack folder<br />
should contain two scripts:<br />
- <tt>builder.sce</tt> (used to build the toolbox, not directly callable by the menu)<br />
- <tt>loader.sce</tt> (called to load the toolbox when it is choosed from the menu)<br />
<br />
== Regression test framework ==<br />
Each block is tested separately with a unit-test to verify no regression was introduced <br />
for both simulation and code-generation. This is done with a regression test framework (in batch-mode).<br />
Testcase SVN repository can be downloaded (read-only) from the following URL:<br />
<tt>svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/scilab_codegen/trunk/testcase</tt><br />
<br />
To launch testcase follow this procedure:<br />
* edit the script "run_scicos_test.sh" to change the environment variables<br />
SCIBASE, TESTBASE and ZIPBASE in accord with the directories used on your PC.<br />
(Please note you can also modify the script to avoid installation of the ScicosPack if already<br />
installed or the SVN checkout if the testcase folder has been already downloaded from the server.)<br />
* run the script to start tests execution<br />
<br />
== Linux support ==<br />
ScicosPack is also available on Linux hosts. <br />
ScicosPack for Linux will be committed and released as soon as possible.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.<br />
<br />
== Support for MSVC2010 and MSVC2012 (only for Windows) ==<br />
ScicosLab 4.4.1 supports Microsoft Visual C\C++ 2010. The presence of the MSVC2010 compiler is automatically recognized and the<br />
MSVC2010 environment is loaded during the ScicosLab initialization.<br />
MSVC2010 is requured by the ScicosPack because it has a number of DLLs builded with MSVC2010 to be linked in the launching step. <br />
ScicosLab doesn't support MSVC2012 directly. <br />
MSVC2012 can be supported writing a new version of the MSVC configuration functions.<br />
See <tt>ScicosLab_441\macros\util\configure_msvc.sci</tt> and similar for further informations.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Installing_scicoslab_and_generating_code_from_a_Scicos_diagramTutorial: Installing scicoslab and generating code from a Scicos diagram2013-09-25T14:34:35Z<p>Erikadds: </p>
<hr />
<div>This is the Wiki page dedicated to the Scicos code generator originally developed by Roberto Bucher from SUPSI Lugano.<br />
<br />
The code of the code generator is distributed under GPL2. The project is currently lead by Roberto Bucher, from SUPSI Lugano, and is hosted on the Evidence web site.<br />
<br />
<br />
<br />
= Scicoslab 4.4.1 and ScicosLab Pack 10.0: code generator for FLEX and EasyLab boards- Installation procedure =<br />
Steps to set up the Scicoslab code generation for FLEX and EasyLab boards<br />
# Download and install Cygwin from the [http://www.cygwin.com/ Cygwin site]. Here is a [http://download.tuxfamily.org/erika/webdownload/eeCygwin_1_7_9.zip minimal installation pack]. Cygwin is required to compile the code generated from your Scicos diagram.<br />
# Download Microsoft Visual C++ 2008 from the [http://www.microsoft.com/it-it/download/details.aspx?id=29 Microsoft Visual C++ site] ([http://www.microsoft.com/express/Downloads/#2008-Visual-CPP or use this link])and install it. It is required from the Evidence Scicoslab pack. <br />
# Download ScicosLab 4.4.1 from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab site] and install it. <br />
# Download Microchip MPLAB IDE from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en019469 MPLAB IDE site] and install it. It is required to program the dsPIC microcontroller mounted on the FLEX board or EasyLab board. Then download a C30 compiler, for example from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010065&part=SW006012 Microchip MPLAB C30 compiler site] and install it. A compiler is required to compile your control application. To program the dsPIC on the Flex board you need a programmer. You can buy a programmer for dsPIC from Microchip site. Programmers suggested are: Microchip MPLAB ICD2 or Microchip MPLAB ICD3. See Microchip for more informations:[http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010046 Microchip programmers site]. While for the EasyLab board the programmer is not required because it is equipped with one on board.<br />
# Download the latest Scicoslab pack from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab pack download page]. Unzip the pack and install it. To install the pack execute the installer.sce script file in ScicosLab (File -> Exec...). (If needed, run ScicosLab with administrator privileges). At the end of the installation restart ScicosLab for the changes to take effect.<br />
# Create and compile your first Scicos diagram (as shown here: [http://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communication An example of code-generation]), flash the microcontroller, test your application and ... enjoy! <br />
<br />
Please note, this version of the ScicosLab pack includes a stand-alone version of RT-Druid and a full version of Erika Enterprise.<br />
If you have any problem please contact us using the [http://erika.tuxfamily.org/forum/ Erika Forum]<br />
<br />
= Your first Scicos application =<br />
<br />
This Chapter will guide you to the creation, compilation and execution<br />
of a first simple Scicos example on a FLEX Demo board (or EasyLab board). The example<br />
created in this tutorial can be found in the directory<br />
<tt>scicos_ee/examples/scicos_flex/Led_sin</tt><br />
<tt>(scicos_ee/examples/scicos_easylab/Led_sin)</tt>.<br />
<br />
inside scicos pack base directory.<br />
<br />
If you are looking for a pre-built example, go directly to the next Section.<br />
<br />
== Creating the Scicos example files ==<br />
<br />
(Note the screenshow may refer to old versions of ScicosLab or Scilab 4.1.2).<br />
<br />
# Please start ScicosLab from the Start menu. The ScicosLab window appears.<br />
# Type <tt>scicos();</tt> as showed below in the Figure, and press Enter.<br />
#: [[File:scilab_splash.png|center|thumb|200px|The Scilab splash screen. Type <tt>scicos();</tt> to start Scicos.]]<br />
# The Scicos windows appears, as showed in Figure<br />
#: [[File:scicos_splash.png|center|thumb|200px|The Scicos splash screen.]]<br />
# You need to compile the Scicos blocks, if you didn't do it yet, in order to get the system working. To do that type these commands in ScicosLab window:<br />
#:cd ("%SCICOSLAB_HOME%\contrib\dspic"); // (%SCICOSLAB_HOME% means the installation path of ScicosLab...)<br />
#:exec ("builder.sce");<br />
#::'''IMPORTANT NOTE''': please check the correctness of this path. Newer Scicos Packs are installed under <tt>...\scicoslab-4.4.1\contrib\scicos_ee\scicos_flex\dspic</tt> <tt>(...\scicoslab-4.4.1\contrib\scicos_ee\scicos_easylab\dspic)</tt><br />
# Select ''Palettes'' from the ''Palette'' menu, as showed in Figure<br />
#: [[File:palette_menu.png|center|thumb|200px|The Palettes.]]<br />
# A little list appear in place of the menu. Select ''FLEX'' (''Easylab''), as showed in Figure<br />
#: [[File:palette_menu2.png|center|thumb|200px|The Palette list.]]<br />
# A windows appears, with some sink blocks specific for the FLEX boards (EasyLab board)<br />
#: [[File:palette.png|center|thumb|200px|The dsPIC Palette.]]<br />
# Single click on the FLEX-LED (EASYLAB-LED) block. The window selection moves to the Scicos window. The mouse now becomes a white rectangle of the dimension of the LED block. Single click somewhere in the white part of the window. A LED block is dropped in the diagram, like in Figure<br />
#: [[File:led.png|center|thumb|200px|The LED block is dropped in the design window.]]<br />
#* '''Note''': If you need to move a block, go over it with the mouse, press ''m'', then move the block and click on the new position!<br />
#* '''Note''': If you need to delete a block or a line, go over it with the mouse, then press ''d''!<br />
#* '''Note''': If some garbage appears on the diagram windos, don't panic! Just press ''r''!<br />
# Open the MCHP16-Sources palette, and repeat the same with the Sine block, placing it on the left of the LED block, as in Figure <br />
#: [[File:sineled.png|center|thumb|200px|Place the Sine block to the left of the LED block.]]<br />
# Link the black triangle of the Sine block to the black triangle of the LED block. To do that, press ''l'', then single click on the triangle of the Sine block (the ''source''), then click again on the triangle of the LED block (the ''sink''). See Figure<br />
#: [[File:link.png|center|thumb|200px|Sine and LED are now linked.]]<br />
# From the MCHP16-Sources Palette, which can be found il the palette list, choose the red clock, and put it on the diagram as shown in Figure<br />
#: [[File:clock.png|center|thumb|200px|Put the Clock block over the Sine and LED blocks.]]<br />
# Now connect the clock signal to the two blocks. To do that, single click on the red triangle of the <tt>clock</tt> block, then single click below it, then single click over the <tt>Sine</tt> block, then click on the red triangle of the <tt>Sine</tt> block. After that, single click on the line below the <tt>clock</tt> block, hit the key 'L' of keyboard, then over the <tt>LED</tt> block, then on the red triangle of the <tt>LED</tt> block. The result is shown in Figure<br />
#: [[File:redlink.png|center|thumb|200px|The Clock block is connected to the Sine and LED blocks.]]<br />
# Single click on the Clock block. Its properties window appears. Leave them untouched, and press OK. You can do the same on the Sine block. The two Figures below show these windows.<br />
#: [[File:clockproperties.png|center|thumb|200px|The Clock block properties.]]<br />
#: [[File:sineproperties.png|center|thumb|200px|The Sine block properties.]]<br />
# The code generator can produce code which only comes from a special block named ''Super Block''. For this reason, we need to create a Super Block enclosing the <tt>Sine</tt> and the <tt>LED</tt> blocks. To do that, select the ''Region to Super Block'' menu item from the ''Diagram'' menu (see Figure below).<br />
#: [[File:region2sb.png|center|thumb|200px|The Region to Super Block menu item.]]<br />
# Then, draw a selection which includes the <tt>Sine</tt>, the <tt>LED</tt>, and the red lines in a way that only ''one'' red line exits the selection, as shown in Figure<br />
#: [[File:sb.png|center|thumb|200px|The selection made to create a Super Block.]]<br />
# As a result, a Super Block is created (see Figure)<br />
#: [[File:sb1.png|center|thumb|200px|The Super Block.]]<br />
#: Which contains the Sine and LED blocks. To see these blocks, just single click on the Super Block, and another window will appear (see Figure). <br />
#: [[File:sb2.png|center|thumb|200px|The contents of the Super Block.]]<br />
# Please note that this window is very similar to the previous one except that the clock object is substituted by a placeholder signed with the number 1.<br />
#* '''Note''': The Diagram containing the Super Block is disabled when the Super Block diagram is displayed. Only one window can be enabled at a time in Scicos. The limitation will be removed in the next version of Scicos.<br />
# It is now time to save the two diagrams. From the ''File'' menu, choose ''Save as''. Save the diagram containing the Super Block as <tt>led_sin.cos</tt>.<br />
<br />
== Generating dsPIC code from a Scicos Diagram ==<br />
<br />
It is now time to generate the code for the example we just created.<br />
<br />
'''Note''': A copy of the file created in the previous steps is included inside the <tt>scicos_examples/led_sin</tt> directory. To open it, double click on the <tt>scicos_examples/led_sin/led_sin.cos</tt> file.<br />
<br />
# Select ''Set Target'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen0.png|center|thumb|200px|The CodeGen menu - Set target.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen3.png|center|thumb|200px|The SetTarget dialog box.]]<br />
# You can specify the target board (board_flex or board_easylab) using the second textbox. Please leave the other options unchanged.<br />
# Select ''FlexCodeGen'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen1.png|center|thumb|200px|The CodeGen menu - Flex code generator.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen2.png|center|thumb|200px|The FlexCodeGen dialog box.]]<br />
# You can specify the block name by modifying the <tt>New block's name</tt> textbox and the directory where all the files will be created by modifying the <tt>Created files Path</tt> textbox. <br />
#* '''IMPORTANT NOTE FOR WINDOWS USERS''': Choose a location where you have write permission. If you start 'ScicosLab' with administrator privileges there are no limitations in the choice of the destination folder.<br />
# Press ''Ok''. As a result, a set of files are generated in the output directory.<br />
# Then, Scicos automatically opens a console window, running in it the following commands:<br />
#* the RT-Druid template generator to instantiate the Scicos template application;<br />
#* the RT-Druid standalone code generator to produce the ERIKA Enterprise configuration files from the generated OIL file;<br />
#* the ''make'' application to compile the code.<br />
# The result of the code generation process is depicted in Figure \ref{fig:console}. <br />
#: [[File:console.png|center|thumb|200px|The compilation console.]]<br />
# The executable file is named <tt>pic30.cof</tt> (older versions of the Scicos-FLEX toolsed had it named <tt>pic30.elf</tt>) and it is located inside the <tt>Debug</tt> directory as usual for all the ERIKA Enterprise applications.<br />
# You can now program your application on your FLEX board. To do that, you need to open MPLABIDE as you usually do to program other ERIKA Enterprise applications. Please refer to the ERIKA Enterprise tutorial for dsPIC for more information.<br />
# Running the code on your FLEX board has the following behavior: the system led on the board flashes with a period of 20 seconds, and a duty cycle of around 6 seconds over 20. The explanation is the following: <br />
#* The system works like a synchronous control system, with a sampling frequency of 0.1 secs<br />
#* The ''Sine'' block output is a sinus with a frequency of 0.05, which correspond to a period of 20 s<br />
#* The LED block is directly linked to the system led, and is programmed to put on the system led when its input is greater than 0.5.<br />
#* Looking at the Figure below, it is clear that the sinus has a value greater than 0.5 for around a third of its period. Given that, the system led is on for around 6 seconds over 20.<br />
#: [[File:graphic.png|center|thumb|200px|A graphic of a Sine and of a constant value 0.5.]]<br />
<br />
= Internals of the genareted code =<br />
<br />
== Templates and customization of the generated application ==<br />
<br />
The default application wich is generated by the Scicos embedded code generator for dsPIC generates a basic application which uses ERIKA Enterprise with the FP kernel, a periodic task and an Alarm triggered by a timer interrupt to activate it.<br />
<br />
In general, it is likely that advanced users would like to customize the application which is generated by the code generator, to add other activities to be executed concurrently with the code generated from the Scicos design. Examples of this activities could be for example background activities for reporting, supervision, display, debug, and so on.<br />
<br />
Implementing such variations is very easy, because the application scheleton used by the code generator is contained inside a RT-Druid template. In particular, the default template is the <tt>pic30_empty_scicos</tt> template stored inside the <tt>examples/pic30/pic30_scicos</tt> directory under the dsPIC examples plugin in the Eclipse installation. The user can add a new template using the following steps:<br />
<br />
# Copy the <tt>examples/pic30/pic30_scicos</tt> directory in another location under the <tt>examples</tt> directory;<br />
# Change the <tt>ID</tt> of the template by modifying the <tt>template.xml</tt> file contained inside the directory. The <tt>ID</tt> is specified in the second line of the XML file as follows: <pre> <evidence_example version="1" ID="pic30_empty_scicos"></pre><br />
# Change the files included in the new template. If you need to add a new file, please remember to add it in the corresponding list in the <tt>template.xml</tt> file.<br />
<br />
Finally, specify the new template when generating the code in the Template textbox.<br />
<br />
== Assumptions of the default template ==<br />
The code generated by the Scilab/Scicos code generator for FLEX uses the template named <tt>pic30_empty_scicos</tt>, and has the following symplifing assumptions:<br />
<br />
# There is a single sampling time T_s in the system;<br />
# T_s is forced to 1 ms;<br />
# Every sampling time specified by the user under the Scicos design will be rounded to a multiple of a millisecond;<br />
# An ERIKA Enterprise counter is linked to the a periodic timer;<br />
# The periodic timer used in the dsPIC hardware is set to raise an interrupt every 1 ms;<br />
# An ERIKA Enterprise alarm is attached to the counter, to periodically activate a task;<br />
# The task body just calls the routines generated by the Scicos code generator. Which executes the functions you specified in the design;<br />
# The PWM object has a fixed period of 1 ms. This means that if the sampling period is a multiple of T_s, then the PWM will repeat the same duty cycle until the PWN value is changed;<br />
# The A/D converter always works ''on demand'', meaning it always executes the following steps:<br />
#* selects a channel;<br />
#* starts the conversion;<br />
#* waits for the end of the conversion (typically max 10 usec)<br />
#* it converts the result in a value from 0.0 V and 3.3 V<br />
<br />
== Installer Key Features ==<br />
The ScicosPack installer is a ScicosLab script executed by users to install/uninstall the ScicosPack.<br />
Key features:<br />
* automatic copy of files (please note, the user has to run ScicosLab with administrator privileges to install the toolbox)<br />
* automatic check of prerequisites <br />
* SMCube compiler configuration<br />
* License check<br />
* Microchip compiler support for Erika\RT-Druid project (certified OSEK micro-kernel)<br />
* automatic build of the ScicosPack sources<br />
* automatic creation of palettes<br />
* automatic loading of blocks-specific help pages<br />
* batch mode supported (for regression test with Jenkins)<br />
<br />
== External libraries linkage ==<br />
ScicosLab supports external DLL/SO linkage. This feature allows the user to link external C functions that are used to model new Scicos blocks for target-specific simulation and code generation.<br />
ScicosLab supports also DLL/SO creation in Windows and Linux hosts. <br />
To do this, ScicosLab automatically configure its environment by adding the required environment variables (MSVC variables in Windows).<br />
Type <tt>help ilib_for_link</tt> for further info (the function path is <tt>ScicosLab_441\macros\util\ilib_for_link.sci</tt>).<br />
External libraries linkage is done by the ScicoLab incremental linker by calling the function <tt>link</tt> (type <tt>help link</tt> for further info).<br />
As decribed in the <tt>link</tt> function's help page, the linkage needs also the C identifiers of the functions to be linked.<br />
Please note, if you create a DLL/SO library starting from an external C++ project (for example using Qt or MSVC++) the<br />
functions to be linked should have C names and not C++ names. This can be obtained using a construct like the following:<br />
At the top of the header file:<br />
<tt><br />
#ifdef __cplusplus<br />
extern "C" {<br />
#endif<br />
</tt><br />
At the bottom of the header file:<br />
<tt><br />
#ifdef __cplusplus<br />
}<br />
#endif<br />
</tt><br />
An example of a block's computational function for simulation is reported below:<br />
<tt><br />
__declspec(dllexport) void block_func(scicos_block *block, int flag)<br />
{<br />
if (flag == OutputUpdate){<br />
/* set output */<br />
block_in_out(block);<br />
}<br />
else if (flag == Ending){<br />
/* termination */ <br />
block_end(block);<br />
}<br />
else if (flag == Initialization){<br />
/* initialization */<br />
block_init(block);<br />
}<br />
}<br />
</tt><br />
For further info about the scicos-block structure look at:<br />
<tt>ScicosLab_441\routines\scicos\scicos_block4.h</tt><br />
<br />
== Code Generation ==<br />
The reference folder is the following:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen</tt><br />
The code-generation logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\FlexCodeGen_.sci</tt><br />
The target selection logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\SetTarget_.sci</tt><br />
Please note, the two logics save the code-generation user preferences in a specific field of the selected superblock.<br />
The superblocks provide to fields, named <tt>void2</tt> and <tt>void3</tt>, that can be used for generic purposes.<br />
New targets and new boards can be added by changing the function <tt>SetTarget_</tt>.<br />
Code generation for embedded application is implemented in the function <tt>FlexCodeGen_</tt>.<br />
Also the code-generation logic may require some minor change to support some specific feature of the new board,<br />
but normally changes are not required.<br />
Each block, designed for code generation, needs a computational target function in addition to the one used for simulation.<br />
The target function should have a prototype and a structure very similar to the computational function reported above.<br />
<br />
== How to add a new Scicos block ==<br />
The first step is to write the interfacing function (.sci) of the block.<br />
The interfacing function is a method that allows to define blocks settings, like the sizes and the types of the<br />
input/output ports of the block , internal states, feed-through properties as well as the internal parameters.<br />
The interfacing function defines also the graphics of the block and specifies the name of the block's <br />
computational function (the C function called in simulation).<br />
Then, the second step is to write the computational function and the target function as described above.<br />
Finally, the last step is to build\link the DLL\SO and to load in Scicos the interfacing function of the block <br />
(see commands like: "lib", "genlib", "exec", "getf", ...).<br />
Refer to this [http://erika.tuxfamily.org/wiki/index.php?title=How_to_add_a_new_Scicos_block_to_ERIKA_Enterprise tutorial] for further information.<br />
<br />
== ScicosPack toolbox loader ==<br />
The ScicosPack can be launched as an external toolbox starting form the ScicosLab menu. To do this, the ScicosPack folder<br />
should contain two scripts:<br />
- <tt>builder.sce</tt> (used to build the toolbox, not directly callable by the menu)<br />
- <tt>loader.sce</tt> (called to load the toolbox when it is choosed from the menu)<br />
<br />
== Regression test framework ==<br />
Each block is tested separately with a unit-test to verify no regression was introduced <br />
for both simulation and code-generation. This is done with a regression test framework (in batch-mode).<br />
Testcase SVN repository can be downloaded (read-only) from the following URL:<br />
<tt>svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/scilab_codegen/trunk/testcase</tt><br />
<br />
To launch testcase follow this procedure:<br />
* edit the script "run_scicos_test.sh" to change the environment variables<br />
SCIBASE, TESTBASE and ZIPBASE in accord with the directories used on your PC.<br />
(Please note you can also modify the script to avoid installation of the ScicosPack if already<br />
installed or the SVN checkout if the testcase folder has been already downloaded from the server.)<br />
* run the script to start tests execution<br />
<br />
== Linux support ==<br />
ScicosPack is also available on Linux hosts. <br />
ScicosPack for Linux will be committed and released as soon as possible.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.<br />
<br />
== Support for MSVC2010 and MSVC2012 (only for Windows) ==<br />
ScicosLab 4.4.1 supports Microsoft Visual C\C++ 2010. The presence of the MSVC2010 compiler is automatically recognized and the<br />
MSVC2010 environment is loaded during the ScicosLab initialization.<br />
MSVC2010 is requured by the ScicosPack because it has a number of DLLs builded with MSVC2010 to be linked in the launching step. <br />
ScicosLab doesn't support MSVC2012 directly. <br />
MSVC2012 can be supported writing a new version of the MSVC configuration functions.<br />
See <tt>ScicosLab_441\macros\util\configure_msvc.sci</tt> and similar for further informations.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Installing_scicoslab_and_generating_code_from_a_Scicos_diagramTutorial: Installing scicoslab and generating code from a Scicos diagram2013-09-25T14:31:46Z<p>Erikadds: /* Internals of the genareted code */</p>
<hr />
<div>This is the Wiki page dedicated to the Scicos code generator originally developed by Roberto Bucher from SUPSI Lugano.<br />
<br />
The code of the code generator is distributed under GPL2. The project is currently lead by Roberto Bucher, from SUPSI Lugano, and is hosted on the Evidence web site.<br />
<br />
<br />
<br />
= Scicoslab 4.4.1 and ScicosLab Pack 10.0: code generator for FLEX and EasyLab boards- Installation procedure =<br />
Steps to set up the Scicoslab code generation for FLEX and EasyLab boards<br />
# Download and install Cygwin from the [http://www.cygwin.com/ Cygwin site]. Here is a [http://download.tuxfamily.org/erika/webdownload/eeCygwin_1_7_9.zip minimal installation pack]. Cygwin is required to compile the code generated from your Scicos diagram.<br />
# Download Microsoft Visual C++ 2008 from the [http://www.microsoft.com/it-it/download/details.aspx?id=29 Microsoft Visual C++ site] ([http://www.microsoft.com/express/Downloads/#2008-Visual-CPP or use this link])and install it. It is required from the Evidence Scicoslab pack. <br />
# Download ScicosLab 4.4.1 from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab site] and install it. <br />
# Download Microchip MPLAB IDE from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en019469 MPLAB IDE site] and install it. It is required to program the dsPIC microcontroller mounted on the FLEX board or EasyLab board. Then download a C30 compiler, for example from the [http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010065&part=SW006012 Microchip MPLAB C30 compiler site] and install it. A compiler is required to compile your control application. To program the dsPIC on the Flex board you need a programmer. You can buy a programmer for dsPIC from Microchip site. Programmers suggested are: Microchip MPLAB ICD2 or Microchip MPLAB ICD3. See Microchip for more informations:[http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010046 Microchip programmers site]. While for the EasyLab board the programmer is not required because it is equipped with one on board.<br />
# Download the latest Scicoslab pack from the [http://erika.tuxfamily.org/scilabscicos.html ScicosLab pack download page]. Unzip the pack and install it. To install the pack execute the installer.sce script file in ScicosLab (File -> Exec...). (If needed, run ScicosLab with administrator privileges). At the end of the installation restart ScicosLab for the changes to take effect.<br />
# Create and compile your first Scicos diagram (as shown here: [http://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communication An example of code-generation]), flash the microcontroller, test your application and ... enjoy! <br />
<br />
Please note, this version of the ScicosLab pack includes a stand-alone version of RT-Druid and a full version of Erika Enterprise.<br />
If you have any problem please contact us using the [http://erika.tuxfamily.org/forum/ Erika Forum]<br />
<br />
= Your first Scicos application =<br />
<br />
This Chapter will guide you to the creation, compilation and execution<br />
of a first simple Scicos example on a FLEX Demo board (or EasyLab board). The example<br />
created in this tutorial can be found in the directory<br />
<tt>scicos_ee/examples/scicos_flex/Led_sin</tt><br />
<tt>(scicos_ee/examples/scicos_easylab/Led_sin)</tt>.<br />
<br />
inside scicos pack base directory.<br />
<br />
If you are looking for a pre-built example, go directly to the next Section.<br />
<br />
== Creating the Scicos example files ==<br />
<br />
(Note the screenshow may refer to old versions of ScicosLab or Scilab 4.1.2).<br />
<br />
# Please start ScicosLab from the Start menu. The ScicosLab window appears.<br />
# Type <tt>scicos();</tt> as showed below in the Figure, and press Enter.<br />
#: [[File:scilab_splash.png|center|thumb|200px|The Scilab splash screen. Type <tt>scicos();</tt> to start Scicos.]]<br />
# The Scicos windows appears, as showed in Figure<br />
#: [[File:scicos_splash.png|center|thumb|200px|The Scicos splash screen.]]<br />
# You need to compile the Scicos blocks, if you didn't do it yet, in order to get the system working. To do that type these commands in ScicosLab window:<br />
#:cd ("%SCICOSLAB_HOME%\contrib\dspic"); // (%SCICOSLAB_HOME% means the installation path of ScicosLab...)<br />
#:exec ("builder.sce");<br />
#::'''IMPORTANT NOTE''': please check the correctness of this path. Newer Scicos Packs are installed under <tt>...\scicoslab-4.4.1\contrib\scicos_ee\scicos_flex\dspic</tt> <tt>(...\scicoslab-4.4.1\contrib\scicos_ee\scicos_easylab\dspic)</tt><br />
# Select ''Palettes'' from the ''Palette'' menu, as showed in Figure<br />
#: [[File:palette_menu.png|center|thumb|200px|The Palettes.]]<br />
# A little list appear in place of the menu. Select ''FLEX'' (''Easylab''), as showed in Figure<br />
#: [[File:palette_menu2.png|center|thumb|200px|The Palette list.]]<br />
# A windows appears, with some sink blocks specific for the FLEX boards (EasyLab board)<br />
#: [[File:palette.png|center|thumb|200px|The dsPIC Palette.]]<br />
# Single click on the FLEX-LED (EASYLAB-LED) block. The window selection moves to the Scicos window. The mouse now becomes a white rectangle of the dimension of the LED block. Single click somewhere in the white part of the window. A LED block is dropped in the diagram, like in Figure<br />
#: [[File:led.png|center|thumb|200px|The LED block is dropped in the design window.]]<br />
#* '''Note''': If you need to move a block, go over it with the mouse, press ''m'', then move the block and click on the new position!<br />
#* '''Note''': If you need to delete a block or a line, go over it with the mouse, then press ''d''!<br />
#* '''Note''': If some garbage appears on the diagram windos, don't panic! Just press ''r''!<br />
# Open the MCHP16-Sources palette, and repeat the same with the Sine block, placing it on the left of the LED block, as in Figure <br />
#: [[File:sineled.png|center|thumb|200px|Place the Sine block to the left of the LED block.]]<br />
# Link the black triangle of the Sine block to the black triangle of the LED block. To do that, press ''l'', then single click on the triangle of the Sine block (the ''source''), then click again on the triangle of the LED block (the ''sink''). See Figure<br />
#: [[File:link.png|center|thumb|200px|Sine and LED are now linked.]]<br />
# From the MCHP16-Sources Palette, which can be found il the palette list, choose the red clock, and put it on the diagram as shown in Figure<br />
#: [[File:clock.png|center|thumb|200px|Put the Clock block over the Sine and LED blocks.]]<br />
# Now connect the clock signal to the two blocks. To do that, single click on the red triangle of the <tt>clock</tt> block, then single click below it, then single click over the <tt>Sine</tt> block, then click on the red triangle of the <tt>Sine</tt> block. After that, single click on the line below the <tt>clock</tt> block, hit the key 'L' of keyboard, then over the <tt>LED</tt> block, then on the red triangle of the <tt>LED</tt> block. The result is shown in Figure<br />
#: [[File:redlink.png|center|thumb|200px|The Clock block is connected to the Sine and LED blocks.]]<br />
# Single click on the Clock block. Its properties window appears. Leave them untouched, and press OK. You can do the same on the Sine block. The two Figures below show these windows.<br />
#: [[File:clockproperties.png|center|thumb|200px|The Clock block properties.]]<br />
#: [[File:sineproperties.png|center|thumb|200px|The Sine block properties.]]<br />
# The code generator can produce code which only comes from a special block named ''Super Block''. For this reason, we need to create a Super Block enclosing the <tt>Sine</tt> and the <tt>LED</tt> blocks. To do that, select the ''Region to Super Block'' menu item from the ''Diagram'' menu (see Figure below).<br />
#: [[File:region2sb.png|center|thumb|200px|The Region to Super Block menu item.]]<br />
# Then, draw a selection which includes the <tt>Sine</tt>, the <tt>LED</tt>, and the red lines in a way that only ''one'' red line exits the selection, as shown in Figure<br />
#: [[File:sb.png|center|thumb|200px|The selection made to create a Super Block.]]<br />
# As a result, a Super Block is created (see Figure)<br />
#: [[File:sb1.png|center|thumb|200px|The Super Block.]]<br />
#: Which contains the Sine and LED blocks. To see these blocks, just single click on the Super Block, and another window will appear (see Figure). <br />
#: [[File:sb2.png|center|thumb|200px|The contents of the Super Block.]]<br />
# Please note that this window is very similar to the previous one except that the clock object is substituted by a placeholder signed with the number 1.<br />
#* '''Note''': The Diagram containing the Super Block is disabled when the Super Block diagram is displayed. Only one window can be enabled at a time in Scicos. The limitation will be removed in the next version of Scicos.<br />
# It is now time to save the two diagrams. From the ''File'' menu, choose ''Save as''. Save the diagram containing the Super Block as <tt>led_sin.cos</tt>.<br />
<br />
== Generating dsPIC code from a Scicos Diagram ==<br />
<br />
It is now time to generate the code for the example we just created.<br />
<br />
'''Note''': A copy of the file created in the previous steps is included inside the <tt>scicos_examples/led_sin</tt> directory. To open it, double click on the <tt>scicos_examples/led_sin/led_sin.cos</tt> file.<br />
<br />
# Select ''Set Target'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen0.png|center|thumb|200px|The CodeGen menu - Set target.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen3.png|center|thumb|200px|The SetTarget dialog box.]]<br />
# You can specify the target board (board_flex or board_easylab) using the second textbox. Please leave the other options unchanged.<br />
# Select ''FlexCodeGen'' from the ''CodeGen'' menu (see Figure).<br />
#: [[File:codegen1.png|center|thumb|200px|The CodeGen menu - Flex code generator.]]<br />
# A window appear, like the one in Figure<br />
#: [[File:codegen2.png|center|thumb|200px|The FlexCodeGen dialog box.]]<br />
# You can specify the block name by modifying the <tt>New block's name</tt> textbox and the directory where all the files will be created by modifying the <tt>Created files Path</tt> textbox. <br />
#* '''IMPORTANT NOTE FOR WINDOWS USERS''': Choose a location where you have write permission. If you start 'ScicosLab' with administrator privileges there are no limitations in the choice of the destination folder.<br />
# Press ''Ok''. As a result, a set of files are generated in the output directory.<br />
# Then, Scicos automatically opens a console window, running in it the following commands:<br />
#* the RT-Druid template generator to instantiate the Scicos template application;<br />
#* the RT-Druid standalone code generator to produce the ERIKA Enterprise configuration files from the generated OIL file;<br />
#* the ''make'' application to compile the code.<br />
# The result of the code generation process is depicted in Figure \ref{fig:console}. <br />
#: [[File:console.png|center|thumb|200px|The compilation console.]]<br />
# The executable file is named <tt>pic30.cof</tt> (older versions of the Scicos-FLEX toolsed had it named <tt>pic30.elf</tt>) and it is located inside the <tt>Debug</tt> directory as usual for all the ERIKA Enterprise applications.<br />
# You can now program your application on your FLEX board. To do that, you need to open MPLABIDE as you usually do to program other ERIKA Enterprise applications. Please refer to the ERIKA Enterprise tutorial for dsPIC for more information.<br />
# Running the code on your FLEX board has the following behavior: the system led on the board flashes with a period of 20 seconds, and a duty cycle of around 6 seconds over 20. The explanation is the following: <br />
#* The system works like a synchronous control system, with a sampling frequency of 0.1 secs<br />
#* The ''Sine'' block output is a sinus with a frequency of 0.05, which correspond to a period of 20 s<br />
#* The LED block is directly linked to the system led, and is programmed to put on the system led when its input is greater than 0.5.<br />
#* Looking at the Figure below, it is clear that the sinus has a value greater than 0.5 for around a third of its period. Given that, the system led is on for around 6 seconds over 20.<br />
#: [[File:graphic.png|center|thumb|200px|A graphic of a Sine and of a constant value 0.5.]]<br />
<br />
= Internals of the genareted code =<br />
<br />
== Templates and customization of the generated application ==<br />
<br />
The default application wich is generated by the Scicos embedded code generator for dsPIC generates a basic application which uses ERIKA Enterprise with the FP kernel, a periodic task and an Alarm triggered by a timer interrupt to activate it.<br />
<br />
In general, it is likely that advanced users would like to customize the application which is generated by the code generator, to add other activities to be executed concurrently with the code generated from the Scicos design. Examples of this activities could be for example background activities for reporting, supervision, display, debug, and so on.<br />
<br />
Implementing such variations is very easy, because the application scheleton used by the code generator is contained inside a RT-Druid template. In particular, the default template is the <tt>pic30_empty_scicos</tt> template stored inside the <tt>examples/pic30/pic30_scicos</tt> directory under the dsPIC examples plugin in the Eclipse installation. The user can add a new template using the following steps:<br />
<br />
# Copy the <tt>examples/pic30/pic30_scicos</tt> directory in another location under the <tt>examples</tt> directory;<br />
# Change the <tt>ID</tt> of the template by modifying the <tt>template.xml</tt> file contained inside the directory. The <tt>ID</tt> is specified in the second line of the XML file as follows: <pre> <evidence_example version="1" ID="pic30_empty_scicos"></pre><br />
# Change the files included in the new template. If you need to add a new file, please remember to add it in the corresponding list in the <tt>template.xml</tt> file.<br />
<br />
Finally, specify the new template when generating the code in the Template textbox.<br />
<br />
== Assumptions of the default template ==<br />
The code generated by the Scilab/Scicos code generator for FLEX uses the template named <tt>pic30_empty_scicos</tt>, and has the following symplifing assumptions:<br />
<br />
# There is a single sampling time T_s in the system;<br />
# T_s is forced to 1 ms;<br />
# Every sampling time specified by the user under the Scicos design will be rounded to a multiple of a millisecond;<br />
# An ERIKA Enterprise counter is linked to the a periodic timer;<br />
# The periodic timer used in the dsPIC hardware is set to raise an interrupt every 1 ms;<br />
# An ERIKA Enterprise alarm is attached to the counter, to periodically activate a task;<br />
# The task body just calls the routines generated by the Scicos code generator. Which executes the functions you specified in the design;<br />
# The PWM object has a fixed period of 1 ms. This means that if the sampling period is a multiple of T_s, then the PWM will repeat the same duty cycle until the PWN value is changed;<br />
# The A/D converter always works ''on demand'', meaning it always executes the following steps:<br />
#* selects a channel;<br />
#* starts the conversion;<br />
#* waits for the end of the conversion (typically max 10 usec)<br />
#* it converts the result in a value from 0.0 V and 3.3 V<br />
<br />
== Installer Key Features ==<br />
The ScicosPack installer is a ScicosLab script executed by users to install/uninstall the ScicosPack.<br />
Key features:<br />
* automatic copy of files (please note, the user has to run ScicosLab with administrator privileges to install the toolbox)<br />
* automatic check of prerequisites <br />
* SMCube compiler configuration<br />
* License check<br />
* Microchip compiler support for Erika\RT-Druid project (certified OSEK micro-kernel)<br />
* automatic build of the ScicosPack sources<br />
* automatic creation of palettes<br />
* automatic loading of blocks-specific help pages<br />
* batch mode supported (for regression test with Jenkins)<br />
<br />
== External libraries linkage **<br />
ScicosLab supports external DLL/SO linkage. This feature allows the user to link external C functions that are used to model new Scicos blocks for target-specific simulation and code generation.<br />
ScicosLab supports also DLL/SO creation in Windows and Linux hosts. <br />
To do this, ScicosLab automatically configure its environment by adding the required environment variables (MSVC variables in Windows).<br />
Type <tt>help ilib_for_link</tt> for further info (the function path is <tt>ScicosLab_441\macros\util\ilib_for_link.sci</tt>).<br />
External libraries linkage is done by the ScicoLab incremental linker by calling the function <tt>link</tt> (type <tt>help link</tt> for further info).<br />
As decribed in the <tt>link</tt> function's help page, the linkage needs also the C identifiers of the functions to be linked.<br />
Please note, if you create a DLL/SO library starting from an external C++ project (for example using Qt or MSVC++) the<br />
functions to be linked should have C names and not C++ names. This can be obtained using a construct like the following:<br />
At the top of the header file:<br />
<tt><br />
#ifdef __cplusplus<br />
extern "C" {<br />
#endif<br />
</tt><br />
At the bottom of the header file:<br />
<tt><br />
#ifdef __cplusplus<br />
}<br />
#endif<br />
</tt><br />
<br />
An example of a block's computational function for simulation is reported below:<br />
<tt><br />
__declspec(dllexport) void block_func(scicos_block *block, int flag)<br />
{<br />
if (flag == OutputUpdate){<br />
/* set output */<br />
block_in_out(block);<br />
}<br />
else if (flag == Ending){<br />
/* termination */ <br />
block_end(block);<br />
}<br />
else if (flag == Initialization){<br />
/* initialization */<br />
block_init(block);<br />
}<br />
}<br />
</tt><br />
For further info about the scicos-block structure look at:<br />
<tt>ScicosLab_441\routines\scicos\scicos_block4.h</tt><br />
<br />
== Code Generation ==<br />
The reference folder is the following:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen</tt><br />
The code-generation logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\FlexCodeGen_.sci</tt><br />
The target selection logic is in the file:<br />
<tt>trunk\ee_scicoslab\scicos_flex\dspic\macros\codegen\SetTarget_.sci</tt><br />
Please note, the two logics save the code-generation user preferences in a specific field of the selected superblock.<br />
The superblocks provide to fields, named <tt>void2</tt> and <tt>void3</tt>, that can be used for generic purposes.<br />
New targets and new boards can be added by changing the function <tt>SetTarget_</tt>.<br />
Code generation for embedded application is implemented in the function <tt>FlexCodeGen_</tt>.<br />
Also the code-generation logic may require some minor change to support some specific feature of the new board,<br />
but normally changes are not required.<br />
Each block, designed for code generation, needs a computational target function in addition to the one used for simulation.<br />
The target function should have a prototype and a structure very similar to the computational function reported above.<br />
<br />
== How to add a new Scicos block ==<br />
The first step is to write the interfacing function (.sci) of the block.<br />
The interfacing function is a method that allows to define blocks settings, like the sizes and the types of the<br />
input/output ports of the block , internal states, feed-through properties as well as the internal parameters.<br />
The interfacing function defines also the graphics of the block and specifies the name of the block's <br />
computational function (the C function called in simulation).<br />
Then, the second step is to write the computational function and the target function as described above.<br />
Finally, the last step is to build\link the DLL\SO and to load in Scicos the interfacing function of the block <br />
(see commands like: "lib", "genlib", "exec", "getf", ...).<br />
Refer to this [http://erika.tuxfamily.org/wiki/index.php?title=How_to_add_a_new_Scicos_block_to_ERIKA_Enterprise tutorial] for further information.<br />
<br />
== ScicosPack toolbox loader ==<br />
The ScicosPack can be launched as an external toolbox starting form the ScicosLab menu. To do this, the ScicosPack folder<br />
should contain two scripts:<br />
- <tt>builder.sce</tt> (used to build the toolbox, not directly callable by the menu)<br />
- <tt>loader.sce</tt> (called to load the toolbox when it is choosed from the menu)<br />
<br />
== Regression test framework ==<br />
Each block is tested separately with a unit-test to verify no regression was introduced <br />
for both simulation and code-generation. This is done with a regression test framework (in batch-mode).<br />
Testcase SVN repository can be downloaded (read-only) from the following URL:<br />
<tt>svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/scilab_codegen/trunk/testcase</tt><br />
To launch testcase follow this procedure:<br />
* edit the script "run_scicos_test.sh" to change the environment variables<br />
SCIBASE, TESTBASE and ZIPBASE in accord with the directories used on your PC.<br />
(Please note you can also modify the script to avoid installation of the ScicosPack if already<br />
installed or the SVN checkout if the testcase folder has been already downloaded from the server.)<br />
* run the script to start tests execution<br />
<br />
== Linux support ==<br />
ScicosPack is also available on Linux hosts. <br />
ScicosPack for Linux will be committed and released as soon as possible.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.<br />
<br />
== Support for MSVC2010 and MSVC2012 (only for Windows) ==<br />
ScicosLab 4.4.1 supports Microsoft Visual C\C++ 2010. The presence of the MSVC2010 compiler is automatically recognized and the<br />
MSVC2010 environment is loaded during the ScicosLab initialization.<br />
MSVC2010 is requured by the ScicosPack because it has a number of DLLs builded with MSVC2010 to be linked in the launching step. <br />
ScicosLab doesn't support MSVC2012 directly. <br />
MSVC2012 can be supported writing a new version of the MSVC configuration functions.<br />
See <tt>ScicosLab_441\macros\util\configure_msvc.sci</tt> and similar for further informations.<br />
Contact us on the [http://erika.tuxfamily.org/forum/ FORUM] for further info.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=How_to_add_a_new_Scicos_block_to_ERIKA_EnterpriseHow to add a new Scicos block to ERIKA Enterprise2013-09-25T14:19:49Z<p>Erikadds: /* Scicoslab 4.4b7 */</p>
<hr />
<div>These are a few notes useful if you want to create a new block in Scicos and the corresponding implementation function in ERIKA Enterprise.<br />
<br />
= Scicoslab 4.4.1 =<br />
<br />
This section describes how to create a new block for Erika Enterprise, and applies the Scicoslab 4.4.1 version of the toolbox.<br />
<br />
Installation steps:<br />
# Install Scicoslab 4.4.1<br />
# Install the last ScicosLab-Pack for FLEX boards<br />
# Install Microsoft Visual Studio Express 2010 (free version is available!)<br />
<br />
Block creation tutorial:<br />
<br />
Preface: directory names are the directory names of my laptop... <br />
# In the folder of interest (e.g. C:\Programmi\scilab\scicoslab_441\contrib\dspic\macros\flex_blocks\FLEX-MTB) write the sci code of your block. Please note the name of your C function must be specified in the scicos_model.sim field.<br />
# If you want to put your new block in a '''new palette''', you need to create a new child folder of flex_blocks, put the block file (.sci file) into and edit '''builder.sce''' and '''loader.sce''' scripts to take this new folder in account.<br />
# To compile block code change the working directory from the scilab console in this way "cd c:/Programmi/scilab/scicoslab_441/contrib/dspic" and then digit the following command "exec builder.sce". You obtain a .bin file.<br />
# To create the new palette file digit the following command "create_palette(folder_path)" (e.g. create_palette("C:\Programmi\scilab\scicoslab_44b7\contrib\dspic\macros\flex_blocks\FLEX-MTB")). You obtain a .cosf file.<br />
# Move the .cosf file in the palettes folder (e.g. C:\Programmi\scilab\scicoslab_441\contrib\dspic\macros\palettes) replacing older file.<br />
# Modify the .scilab configuration file in your $(HOME)/ScicosLab/{version}, to add the new palette to scicos' palettes sub-menu.<br />
# Modify the file named "symbols" inserting the name of your block and the symbols you want to be associated.<br />
# Write your C files and place them in the scicos folders inside Erika Enterprise tree. (e.g. C:\Evidence\eclipse\plugins\com.eu.evidence.ee_1.5.1.201005181137\ee_base\contrib\scicos\inc\pic30\mycode.h C:\Evidence\eclipse\plugins\com.eu.evidence.ee_1.5.1.201005181137\ee_base\contrib\scicos\src\pic30\mycode.c). Please check if you must modify the contrib\scicos\cfg\cfg.mk to tell the compiler that your file must be compiled!<br />
# Create a DLL with the computational function of your block to be used for simulation, and link the DLL library in ScicosLab (type "help link" for further info). <br />
# Create a scicos diagram and try to genereate the code.<br />
<br />
If your application works fine you have successfully completed this tutorial. Congratulations!!! ;-)<br />
<br />
= Scilab 4.1.2 =<br />
<br />
This information derives from a post in the ERIKA Forum, and applies the Scilab 4.1.2 version of the toolbox.<br />
# Preface<br />
## Directory names are the directory names of my laptop...<br />
## Use the zip file attached. for each step, there are a few files to look at<br />
## I had to edit the post to substitute backslash with slashes<br />
# Install Scilab 4.1.2<br />
# Install the Scicos Pack for the FLEX boards<br />
# Install Microsoft Visual Studio Express 2008<br />
# [http://www.evidence.eu.com/download/scicos/MSVC2008_Patch.zip Install these patches] in Scilab 4.1.2. They are needed to let Scilab discover the Visual studio compiler<br />
# NMake<br />
## install NMake from http://support.microsoft.com/default.aspx?scid=kb;en-us;Q132084<br />
## rename the executable file in nmake.exe and copy it into C:/Windows<br />
# Update the files<br />
## You need to create the block file. You can use Roberto's block editor http://web.dti.supsi.ch/~bucher/ . Or check out the block example at http://www.evidence.eu.com/component/option,com_fireboard/Itemid,262/func,view/id,6/catid,3/<br />
## add into the C:/Programmi/scilab-4.1.2/contrib/dspic/macros/name one line with the file name<br />
## in C:/Programmi/scilab-4.1.2/contrib/dspic/bulder.sce , we have to comment a few lines, because we are not going to compile the .c files distributed with the package. in particular, comment from the line "cd(ROUTINES)" to the one but last line (leave only the "cd('..')"<br />
# Compile<br />
## open scilab 4.1.2<br />
## from the scilab console, "cd c:/Programmi/scilab-4.1.2/contrib/dspic"<br />
## from the scilab console, "exec builder.sce"<br />
# you get an output similar to the following one<br />
#:--------------------------------------------------------------------<br />
#:___________________________________________<br />
#:scilab-4.1.1<br />
#:<br />
#:Copyright (c) 1989-2007<br />
#:Consortium Scilab (INRIA, ENPC)<br />
#:___________________________________________<br />
#:<br />
#:<br />
#:Startup execution:<br />
#:loading initial environment<br />
#:shared archive loaded<br />
#:_link_ done<br />
#:<br />
#:Scicos-FLEX Ready<br />
#:<br />
#:-->cd c:/Programmi/scilab-4.1.1/contrib/dspic<br />
#:ans =<br />
#:<br />
#:c:/Programmi/scilab-4.1.1/contrib/dspic<br />
#:<br />
#:-->exec builder.sce<br />
#:<br />
#:-->mode(-1);<br />
#:<br />
#:--><br />
#:<br />
#:--------------------------------------------------------------------<br />
# Add the block to the scicos Palette<br />
## "cd macros"<br />
## open scicos by typing "scicos();"<br />
## Menu "Diagram/Load", load the file "dspic.cosf"<br />
## Menu "Edit/Add New block", specify the file name "dspic_getfreq", press ok and place the block inside the palette where you want<br />
## menu "Diagram/Save As", and give the name "dspic.cosf" - with the final "f"!!!<br />
## close Scicos and Scilab<br />
## now if you open again scicos, the dspic palette should have the dspic_getfreq block.<br />
# Configuring Erika Enterprise<br />
## copy the getfreq.c file inside "C:/Programmi/Evidence/ee/contrib/scicos/src/pic30"<br />
## add getfreq.c inside "C:/Programmi/Evidence/ee/contrib/scicos/cfg/cfg.mk" (see file attached for an example)<br />
# Create a scicos example<br />
## Follow the Scicos tutorial, but use the getfreq instead of the Sine (see files in the zip)<br />
## compile and enjoy!</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Freescale_S12Freescale S122013-05-23T08:46:25Z<p>Erikadds: /* Freescale S12 support */</p>
<hr />
<div>= Freescale S12 support =<br />
ERIKA Enterprise supports Freescale HCS12 microcontrollers. <br />
The support for RT-Druid is now available .<br><br />
The HCS12 support includes: <br />
# support for '''COSMIC''' compiler (only for HCS12XS, since Erika release 1.5.0) <br />
# support for '''CODEWARRIOR CWS12v5.1''' compiler (since Erika release 1.6.0).<br />
# support for single and multi stack configurations.<br />
# ISR interrupt supported.<br />
# support for Freescale HIWAVE Debugger.<br />
<br />
* '''Supported compiler'''<br />
** COSMIC C cross compiler and ELF module generation for debugging information.<br />
** CODEWARRIOR CWS12v5.1 compiler and ELF module generation for debugging information (Note: For some MCU is recommended to install the compiler updates available on the Freescale website).<br />
::* CODEWARRIOR compiler is enabled adding this option in the conf.oil file:<br />
EE_OPT = "__CODEWARRIOR__";<br />
::* If the compiler evaluation license is expired, you may have to add also this option to avoid syntax errors during the compilation:<br />
EE_OPT = "CW_EVAL_VERSION"; <br />
* '''Mode of operation'''<br />
** ''Mono-stack'': The Monostack configuration of the ERIKA Kernel models the fact that all tasks and ISRs in the system share the same stack.<br />
** ''Multi-stack'': Every thread can have its private stack, or it can share it with other threads. <br />
<br />
* '''Handling of paging registers'''<br />
:The compiler supports bank switching for code and data, using the internal window mechanism provided by the HCS12 processor.<br />
:Bank switching mechanism delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.<br />
:Bank switching is supported via:<br />
:- @far type qualifier to describe a function relocated in a different bank. Calling such a function implies a special calling <br />
:sequence, and a special return sequence. Such a function has to be defined @far and referenced as @far in all the files using <br />
:it. The COSMIC compiler also provides a specific option +modf to automatically consider all the functions to be @far. The @far type <br />
:modifier is also used to declared variables allocated in a data bank.<br />
:- Linker options are required to ensure proper physical and logical addresses computations. The linker is also able to <br />
:automatically fill banks without any need to take care of the page boundaries.<br />
<br />
= CPUs =<br />
* '''S12 Hardware Abstraction Layer''' (since Erika revision 1531): S12 HAL now integrates the Erika HAL common files (see [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/cpu/common/ 'pkg/cpu/common'] folder and [http://erika.tuxfamily.org/wiki/index.php?title=Common_files_for_the_HAL Common_files_for_the_HAL] for further info). This feature simplifies future extensions for other S12 devices and ensures greater code stability against changes to the kernel code.<br />
* '''Nesting of interrupts''':<br />
** ''MC9s12XS128'': The IPL bits allow the nesting of interrupts, blocking interrupts of an equal or lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.<br />
** ''MC9S12G128'': <pre style="color:red">WARNING: MC9S12G128 doesn't support IPL mechanism.</pre> To enable the nesting of interrupts in the code, the user should clear I bit (in the CCR register) inside the interrupt service routine and after the peripheral interrupt flag has been cleared. If the I bit is cleared before the peripheral interrupt flag has been cleared the CPU restarts the interrupt creating an infinite loop. For this reason I-bit cannot be cleared inside Erika HAL files and this task is left to the user. To enable the compilation of the code for the nesting of interrupts the symbol<br />
__ALLOW_NESTED_IRQ__<br />
must be defined.<br />
Note: If the kernel type is FP the nesting of the interrupts can be enabled in this way:<br />
KERNEL_TYPE = FP{<br />
NESTED_IRQ = TRUE;<br />
}; <br />
otherwise the default case is FALSE and the nesting of the interrupts is disabled.<br />
<br />
= MCUs =<br />
<br />
* The MCUs currently supported are the following:<br />
** ''Freescale'' '''MC9S12XS128'''<br />
** ''Freescale'' '''MC9S12G128'''<br />
** ''Freescale'' '''MC9S12G48'''<br />
** ''Freescale'' '''MC9S12GN16'''<br />
** ''Freescale'' '''MC9S12GN32'''<br />
** ''Freescale'' '''MC9S12GN48'''<br />
<br />
* List of functions:<br />
** ''Periodic interrupt timer''<br />
*** void EE_pit0_init( unsigned char pitmtld0, unsigned char pitld0, unsigned char prio ); // To init PIT0<br />
*** void EE_pit0_close( void ); // To close PIT0<br />
*** void EE_pit0_clear_ISRflag( void ); // To clean PIT0 ISR flag <br />
** ''Serial communication interface''<br />
*** void EE_sci_open(unsigned char sci_num, unsigned long int baudrate); // Open the serial interface. Requires: EE_set_peripheral_frequency_mhz(f_mhz) <br />
*** void EE_sci_close(unsigned char sci_num); // To close the serial interface<br />
*** Bool EE_sci_send_byte(unsigned char sci_num, unsigned char buffer); // To send a byte<br />
*** Bool EE_sci_send_string(unsigned char sci_num, const char* s, unsigned int num); // to send a string<br />
*** Bool EE_sci_send_bytes(unsigned char sci_num, char* v, unsigned int num); // To send a vector of bytes<br />
*** Bool EE_sci_get_byte(unsigned char sci_num, unsigned char *buffer); // to get a byte<br />
*** Bool EE_sci_getcheck(unsigned char sci_num); // to check the serial reception of a byte<br />
** ''Timer''<br />
*** int EE_timer_init_us(EE_UINT16 tim_id, EE_UINT32 period_us, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** int EE_timer_init_ms(EE_UINT16 tim_id, EE_UINT16 period_ms, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** void EE_timer_start() // start timer<br />
*** void EE_timer_stop() // stop timer<br />
*** void EE_timer_reset() // reset timer<br />
*** void EE_timer_clear_ISRflag(EE_UINT16 tim_id) // clear interrrupt flag<br />
*** EE_UINT16 EE_timer_get_counter() // get counter<br />
*** void EE_timer_enable_ISR(EE_UINT16 tim_id, EE_UINT8 isr_mode) // enable IRQ<br />
** void EE_timer_disable_ISR(EE_UINT16 tim_id) // disable IRQ<br />
<br />
= Boards =<br />
<br />
* The boards currently supported are the following:<br />
** ''SofTec Microsystems'' '''DEMO9S12XSFAME''' demo board.<br />
** ''Freescale Axiom'' '''TWRS12G128''' evaluation board.<br />
<br />
<br />
* '''DEMO9S12XSFAME''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/hs12xs_demo9s12xsfame/ demo9s12xsfame])<br />
** void EE_demo9s12xsfame_leds_init(void); // To configure the leds port <br />
** void EE_demo9s12xsfame_leds( EE_UINT8 data ); // To set the led port vaules <br />
** void EE_demo9s12xsfame_led_0_on(void); // To turn on LED0<br />
** void EE_demo9s12xsfame_led_0_off(void); // To turn off LED0<br />
** void EE_demo9s12xsfame_led_1_on(void); // To turn on LED1<br />
** void EE_demo9s12xsfame_led_1_off(void); // To turn off LED1<br />
** void EE_demo9s12xsfame_led_2_on(void); // To turn on LED2<br />
** void EE_demo9s12xsfame_led_2_off(void); // To turn off LED2<br />
** void EE_demo9s12xsfame_led_3_on(void); // To turn on LED3<br />
** void EE_demo9s12xsfame_led_3_off(void); // To turn off LED3<br />
** void EE_demo9s12xsfame_leds_on(void); // To turn on all the leds<br />
** void EE_demo9s12xsfame_leds_off(void); // To turn off all the leds<br />
** void EE_demo9s12xsfame_buttons_init( EE_UINT8 bx, EE_UINT8 prio ); // To init the buttons port<br />
** void EE_demo9s12xsfame_buttons_close( void ); // To reset the buttons port<br />
** void EE_demo9s12xsfame_buttons_disable_interrupts( EE_UINT8 bx ); // To disable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_enable_interrupts( EE_UINT8 bx ); // To enable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_clear_ISRflag( EE_UINT8 bx ); // To clear button ISR flag<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B0( void ); // To get the BUTTON0 value<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B1( void ); // To get the BUTTON1 value<br />
** void EE_demo9s12xsfame_adc_init( unsigned char res, unsigned char numconvseq ); // To init ADC<br />
** void EE_demo9s12xsfame_adc_convert( void ); // To start conversion<br />
** unsigned int EE_demo9s12xsfame_adc_getvalue( unsigned int adcch ); // To get a value<br />
** void EE_demo9s12xsfame_adc_close( void ); // To close ADC<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_light( void ); // To get light sensor value<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_pot( void ); // To get potentiometer value<br />
<br />
<br />
* '''TWRS12G128''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/twrs12g128/ twrs12g128])<br />
** void EE_leds_init() or EE_twrs12g128_leds_init()<br />
** void EE_leds(EE_UINT8 data) or EE_twrs12g128_leds(EE_UINT8 data)<br />
** void EE_led_1_on() or EE_twrs12g128_led_1_on() <br />
** void EE_led_1_off() or EE_twrs12g128_led_1_off() <br />
** void EE_led_2_on() or EE_twrs12g128_led_2_on() <br />
** void EE_led_2_off() or EE_twrs12g128_led_2_off() <br />
** void EE_led_3_on() or EE_twrs12g128_led_3_on() <br />
** void EE_led_3_off() or EE_twrs12g128_led_3_off() <br />
** void EE_led_4_on() or EE_twrs12g128_led_4_on() <br />
** void EE_led_4_off() or EE_twrs12g128_led_4_off()<br />
** void EE_led_1_toggle() or EE_twrs12g128_led_1_toggle()<br />
** void EE_led_2_toggle() or EE_twrs12g128_led_2_toggle()<br />
** void EE_led_3_toggle() or EE_twrs12g128_led_3_toggle()<br />
** void EE_led_4_toggle() or EE_twrs12g128_led_4_toggle()<br />
** void EE_leds_on() or EE_twrs12g128_leds_on() <br />
** void EE_leds_off() or EE_twrs12g128_leds_off() <br />
** void EE_buttons_init(EE_UINT8 bx) or EE_twrs12g128_buttons_init(EE_UINT8 bx)<br />
** void EE_buttons_close or EE_twrs12g128_buttons_close()<br />
** EE_UINT8 EE_button_get_B1() or EE_twrs12g128_button_get_B1()<br />
** EE_UINT8 EE_button_get_B2() or EE_twrs12g128_button_get_B2()<br />
** EE_UINT8 EE_button_get_B3() or EE_twrs12g128_button_get_B3()<br />
** EE_UINT8 EE_button_get_B4() or EE_twrs12g128_button_get_B4()<br />
<br />
= Examples =<br />
<br />
* The examples and tests are available in this folders:<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12xs/ S12XS examples]<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12g/ S12G examples]<br />
<br />
= Download and install =<br />
<br />
RT-Druid and Erika Enterprise RTOS (version 1.6.0), for Microsoft Windows, can be freely downloaded from the following web address:<br />
* [http://download.tuxfamily.org/erika/webdownload/eeb_gpl/EE_160_Win.zip EE_160_Win.zip]<br />
<br />
Once downloaded, extract all the files contained in it and copy the folder named ''eclipse'' in your preferred directory on your PC (a recommended path is: C:\Evidence\).<br />
Now, launch the program by double-clicking on the executable ''eclipse.exe''inside the ''C:\Evidence\eclipse'' folder and choose the path of your workspace.<br />
The workspace is the default working directory in which the projects will be created. <br />
<br />
<br />
If you want to download only a selected revision of the kernel, open the Cygwin shell and get an anonymous SVN checkout typing this command:<br />
svn co svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/ee/trunk/ee -r number_of_revision<br />
<br />
Note: <br />
Cygwin can be downloaded from this web site: http://www.cygwin.com/ <br />
To use SVN, the Cygwin SVN package must to be installed using the Cygwin Setup utility.<br />
<br />
<br />
To update your RT-DRUID version:<br />
* Open the “Help” menu item and selecting “Install New Software” (see image below).<br />
[[image:install_new_sw.PNG|center|100px]]<br />
* Then add, for example, the following path: [http://download.tuxfamily.org/erika/webdownload/rtdruid_160_nb/]<br />
* To add a new web address, clicking on “Add” and write the desired address in the filed “Location” (see image below).<br />
[[image:add_web_address.PNG|center|100px]]<br />
* Select all the plugins and click on the “Next” button. Then click again on “Next”, read the conditions and ''in case'' accept them by clicking on the “Finish” button.<br />
* Wait for the completion of the update and restart before using the software.<br />
<br />
<br />
'''Warnings and recommendations''' <br />
* For a fast installation deselect ''Contact all update sites during install to find required software''.<br />
* The revision '''1543''' of '''RT-Druid''' and '''Erika''' has been tested on the MODISTARC testcase, so this version is recommended.<br />
* However, the new Erika HCS12 package can work also with the previous versions of RT-Druid.<br />
<br />
= How to build a project in RT-DRUID =<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12XS]]<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12G]]<br />
* [[Tutorial: S12XS - First installation and application compilation on Windows]]<br />
* [[OIL example for Freescale S12]]<br />
<br />
= How to run MODISTARC regression tests =<br />
* [[A brief description on how to run MODISTARC regression tests for Freescale S12XS]]<br />
<br />
<br />
[[Category:Supported Devices]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Freescale_S12Freescale S122013-05-23T08:42:53Z<p>Erikadds: /* MCUs */</p>
<hr />
<div>= Freescale S12 support =<br />
ERIKA Enterprise supports Freescale HCS12 microcontrollers. <br />
The support for RT-Druid is now available .<br><br />
The HCS12 support includes: <br />
# support for '''COSMIC''' compiler (only for HCS12XS, since Erika release 1.5.0) <br />
# support for '''CODEWARRIOR CWS12v5.1''' compiler (since Erika release 1.6.0).<br />
# support for single and multi stack configurations.<br />
# ISR interrupt supported.<br />
# support for Freescale HIWAVE Debugger.<br />
<br />
* '''Supported compiler'''<br />
** COSMIC C cross compiler and ELF module generation for debugging information.<br />
** CODEWARRIOR CWS12v5.1 compiler and ELF module generation for debugging information.<br />
::* CODEWARRIOR compiler is enabled adding this option in the conf.oil file:<br />
EE_OPT = "__CODEWARRIOR__";<br />
::* If the compiler evaluation license is expired, you may have to add also this option to avoid syntax errors during the compilation:<br />
EE_OPT = "CW_EVAL_VERSION"; <br />
* '''Mode of operation'''<br />
** ''Mono-stack'': The Monostack configuration of the ERIKA Kernel models the fact that all tasks and ISRs in the system share the same stack.<br />
** ''Multi-stack'': Every thread can have its private stack, or it can share it with other threads. <br />
<br />
* '''Handling of paging registers'''<br />
:The compiler supports bank switching for code and data, using the internal window mechanism provided by the HCS12 processor.<br />
:Bank switching mechanism delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.<br />
:Bank switching is supported via:<br />
:- @far type qualifier to describe a function relocated in a different bank. Calling such a function implies a special calling <br />
:sequence, and a special return sequence. Such a function has to be defined @far and referenced as @far in all the files using <br />
:it. The COSMIC compiler also provides a specific option +modf to automatically consider all the functions to be @far. The @far type <br />
:modifier is also used to declared variables allocated in a data bank.<br />
:- Linker options are required to ensure proper physical and logical addresses computations. The linker is also able to <br />
:automatically fill banks without any need to take care of the page boundaries.<br />
<br />
= CPUs =<br />
* '''S12 Hardware Abstraction Layer''' (since Erika revision 1531): S12 HAL now integrates the Erika HAL common files (see [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/cpu/common/ 'pkg/cpu/common'] folder and [http://erika.tuxfamily.org/wiki/index.php?title=Common_files_for_the_HAL Common_files_for_the_HAL] for further info). This feature simplifies future extensions for other S12 devices and ensures greater code stability against changes to the kernel code.<br />
* '''Nesting of interrupts''':<br />
** ''MC9s12XS128'': The IPL bits allow the nesting of interrupts, blocking interrupts of an equal or lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.<br />
** ''MC9S12G128'': <pre style="color:red">WARNING: MC9S12G128 doesn't support IPL mechanism.</pre> To enable the nesting of interrupts in the code, the user should clear I bit (in the CCR register) inside the interrupt service routine and after the peripheral interrupt flag has been cleared. If the I bit is cleared before the peripheral interrupt flag has been cleared the CPU restarts the interrupt creating an infinite loop. For this reason I-bit cannot be cleared inside Erika HAL files and this task is left to the user. To enable the compilation of the code for the nesting of interrupts the symbol<br />
__ALLOW_NESTED_IRQ__<br />
must be defined.<br />
Note: If the kernel type is FP the nesting of the interrupts can be enabled in this way:<br />
KERNEL_TYPE = FP{<br />
NESTED_IRQ = TRUE;<br />
}; <br />
otherwise the default case is FALSE and the nesting of the interrupts is disabled.<br />
<br />
= MCUs =<br />
<br />
* The MCUs currently supported are the following:<br />
** ''Freescale'' '''MC9S12XS128'''<br />
** ''Freescale'' '''MC9S12G128'''<br />
** ''Freescale'' '''MC9S12G48'''<br />
** ''Freescale'' '''MC9S12GN16'''<br />
** ''Freescale'' '''MC9S12GN32'''<br />
** ''Freescale'' '''MC9S12GN48'''<br />
<br />
* List of functions:<br />
** ''Periodic interrupt timer''<br />
*** void EE_pit0_init( unsigned char pitmtld0, unsigned char pitld0, unsigned char prio ); // To init PIT0<br />
*** void EE_pit0_close( void ); // To close PIT0<br />
*** void EE_pit0_clear_ISRflag( void ); // To clean PIT0 ISR flag <br />
** ''Serial communication interface''<br />
*** void EE_sci_open(unsigned char sci_num, unsigned long int baudrate); // Open the serial interface. Requires: EE_set_peripheral_frequency_mhz(f_mhz) <br />
*** void EE_sci_close(unsigned char sci_num); // To close the serial interface<br />
*** Bool EE_sci_send_byte(unsigned char sci_num, unsigned char buffer); // To send a byte<br />
*** Bool EE_sci_send_string(unsigned char sci_num, const char* s, unsigned int num); // to send a string<br />
*** Bool EE_sci_send_bytes(unsigned char sci_num, char* v, unsigned int num); // To send a vector of bytes<br />
*** Bool EE_sci_get_byte(unsigned char sci_num, unsigned char *buffer); // to get a byte<br />
*** Bool EE_sci_getcheck(unsigned char sci_num); // to check the serial reception of a byte<br />
** ''Timer''<br />
*** int EE_timer_init_us(EE_UINT16 tim_id, EE_UINT32 period_us, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** int EE_timer_init_ms(EE_UINT16 tim_id, EE_UINT16 period_ms, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** void EE_timer_start() // start timer<br />
*** void EE_timer_stop() // stop timer<br />
*** void EE_timer_reset() // reset timer<br />
*** void EE_timer_clear_ISRflag(EE_UINT16 tim_id) // clear interrrupt flag<br />
*** EE_UINT16 EE_timer_get_counter() // get counter<br />
*** void EE_timer_enable_ISR(EE_UINT16 tim_id, EE_UINT8 isr_mode) // enable IRQ<br />
** void EE_timer_disable_ISR(EE_UINT16 tim_id) // disable IRQ<br />
<br />
= Boards =<br />
<br />
* The boards currently supported are the following:<br />
** ''SofTec Microsystems'' '''DEMO9S12XSFAME''' demo board.<br />
** ''Freescale Axiom'' '''TWRS12G128''' evaluation board.<br />
<br />
<br />
* '''DEMO9S12XSFAME''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/hs12xs_demo9s12xsfame/ demo9s12xsfame])<br />
** void EE_demo9s12xsfame_leds_init(void); // To configure the leds port <br />
** void EE_demo9s12xsfame_leds( EE_UINT8 data ); // To set the led port vaules <br />
** void EE_demo9s12xsfame_led_0_on(void); // To turn on LED0<br />
** void EE_demo9s12xsfame_led_0_off(void); // To turn off LED0<br />
** void EE_demo9s12xsfame_led_1_on(void); // To turn on LED1<br />
** void EE_demo9s12xsfame_led_1_off(void); // To turn off LED1<br />
** void EE_demo9s12xsfame_led_2_on(void); // To turn on LED2<br />
** void EE_demo9s12xsfame_led_2_off(void); // To turn off LED2<br />
** void EE_demo9s12xsfame_led_3_on(void); // To turn on LED3<br />
** void EE_demo9s12xsfame_led_3_off(void); // To turn off LED3<br />
** void EE_demo9s12xsfame_leds_on(void); // To turn on all the leds<br />
** void EE_demo9s12xsfame_leds_off(void); // To turn off all the leds<br />
** void EE_demo9s12xsfame_buttons_init( EE_UINT8 bx, EE_UINT8 prio ); // To init the buttons port<br />
** void EE_demo9s12xsfame_buttons_close( void ); // To reset the buttons port<br />
** void EE_demo9s12xsfame_buttons_disable_interrupts( EE_UINT8 bx ); // To disable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_enable_interrupts( EE_UINT8 bx ); // To enable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_clear_ISRflag( EE_UINT8 bx ); // To clear button ISR flag<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B0( void ); // To get the BUTTON0 value<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B1( void ); // To get the BUTTON1 value<br />
** void EE_demo9s12xsfame_adc_init( unsigned char res, unsigned char numconvseq ); // To init ADC<br />
** void EE_demo9s12xsfame_adc_convert( void ); // To start conversion<br />
** unsigned int EE_demo9s12xsfame_adc_getvalue( unsigned int adcch ); // To get a value<br />
** void EE_demo9s12xsfame_adc_close( void ); // To close ADC<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_light( void ); // To get light sensor value<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_pot( void ); // To get potentiometer value<br />
<br />
<br />
* '''TWRS12G128''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/twrs12g128/ twrs12g128])<br />
** void EE_leds_init() or EE_twrs12g128_leds_init()<br />
** void EE_leds(EE_UINT8 data) or EE_twrs12g128_leds(EE_UINT8 data)<br />
** void EE_led_1_on() or EE_twrs12g128_led_1_on() <br />
** void EE_led_1_off() or EE_twrs12g128_led_1_off() <br />
** void EE_led_2_on() or EE_twrs12g128_led_2_on() <br />
** void EE_led_2_off() or EE_twrs12g128_led_2_off() <br />
** void EE_led_3_on() or EE_twrs12g128_led_3_on() <br />
** void EE_led_3_off() or EE_twrs12g128_led_3_off() <br />
** void EE_led_4_on() or EE_twrs12g128_led_4_on() <br />
** void EE_led_4_off() or EE_twrs12g128_led_4_off()<br />
** void EE_led_1_toggle() or EE_twrs12g128_led_1_toggle()<br />
** void EE_led_2_toggle() or EE_twrs12g128_led_2_toggle()<br />
** void EE_led_3_toggle() or EE_twrs12g128_led_3_toggle()<br />
** void EE_led_4_toggle() or EE_twrs12g128_led_4_toggle()<br />
** void EE_leds_on() or EE_twrs12g128_leds_on() <br />
** void EE_leds_off() or EE_twrs12g128_leds_off() <br />
** void EE_buttons_init(EE_UINT8 bx) or EE_twrs12g128_buttons_init(EE_UINT8 bx)<br />
** void EE_buttons_close or EE_twrs12g128_buttons_close()<br />
** EE_UINT8 EE_button_get_B1() or EE_twrs12g128_button_get_B1()<br />
** EE_UINT8 EE_button_get_B2() or EE_twrs12g128_button_get_B2()<br />
** EE_UINT8 EE_button_get_B3() or EE_twrs12g128_button_get_B3()<br />
** EE_UINT8 EE_button_get_B4() or EE_twrs12g128_button_get_B4()<br />
<br />
= Examples =<br />
<br />
* The examples and tests are available in this folders:<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12xs/ S12XS examples]<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12g/ S12G examples]<br />
<br />
= Download and install =<br />
<br />
RT-Druid and Erika Enterprise RTOS (version 1.6.0), for Microsoft Windows, can be freely downloaded from the following web address:<br />
* [http://download.tuxfamily.org/erika/webdownload/eeb_gpl/EE_160_Win.zip EE_160_Win.zip]<br />
<br />
Once downloaded, extract all the files contained in it and copy the folder named ''eclipse'' in your preferred directory on your PC (a recommended path is: C:\Evidence\).<br />
Now, launch the program by double-clicking on the executable ''eclipse.exe''inside the ''C:\Evidence\eclipse'' folder and choose the path of your workspace.<br />
The workspace is the default working directory in which the projects will be created. <br />
<br />
<br />
If you want to download only a selected revision of the kernel, open the Cygwin shell and get an anonymous SVN checkout typing this command:<br />
svn co svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/ee/trunk/ee -r number_of_revision<br />
<br />
Note: <br />
Cygwin can be downloaded from this web site: http://www.cygwin.com/ <br />
To use SVN, the Cygwin SVN package must to be installed using the Cygwin Setup utility.<br />
<br />
<br />
To update your RT-DRUID version:<br />
* Open the “Help” menu item and selecting “Install New Software” (see image below).<br />
[[image:install_new_sw.PNG|center|100px]]<br />
* Then add, for example, the following path: [http://download.tuxfamily.org/erika/webdownload/rtdruid_160_nb/]<br />
* To add a new web address, clicking on “Add” and write the desired address in the filed “Location” (see image below).<br />
[[image:add_web_address.PNG|center|100px]]<br />
* Select all the plugins and click on the “Next” button. Then click again on “Next”, read the conditions and ''in case'' accept them by clicking on the “Finish” button.<br />
* Wait for the completion of the update and restart before using the software.<br />
<br />
<br />
'''Warnings and recommendations''' <br />
* For a fast installation deselect ''Contact all update sites during install to find required software''.<br />
* The revision '''1543''' of '''RT-Druid''' and '''Erika''' has been tested on the MODISTARC testcase, so this version is recommended.<br />
* However, the new Erika HCS12 package can work also with the previous versions of RT-Druid.<br />
<br />
= How to build a project in RT-DRUID =<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12XS]]<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12G]]<br />
* [[Tutorial: S12XS - First installation and application compilation on Windows]]<br />
* [[OIL example for Freescale S12]]<br />
<br />
= How to run MODISTARC regression tests =<br />
* [[A brief description on how to run MODISTARC regression tests for Freescale S12XS]]<br />
<br />
<br />
[[Category:Supported Devices]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communicationAmazing Ball Control System: An example of PID control and UDP communication2012-08-27T13:02:24Z<p>Erikadds: </p>
<hr />
<div>Step 1:<br />
* Open ScicosLab 4.4b7, the Scicos-FLEX pack is recognized by the program (refer Fig. 1).<br />
: Change the working directory to “C:\Programmi\scilab\scicoslab_44b7\contrib\dspic”.<br />
: Type exec builder.sce to build any application of the pack.<br />
<br />
[[image:scicoslab1.png]]<br />
::::::: Figure 1 – ScicosLab<br />
<br />
Step 2:<br />
* Open file “pid_ctrl_codegen_udp_tuning_square_circle.cos” (refer Fig. 2) in Scicos.<br />
: The .cos file contains the schematic for the FLEX embedded code generation (with SCICOS).<br />
: This application is for tuning coefficients of the PID control for improving system<br />
: performance.<br />
<br />
[[image:scicoslab2.png]]<br />
::::::: Figure 2 – Control system schematic<br />
<br />
Step 3:<br />
* Click menu CodeGen and select FlexCodeGen.<br />
: Click on the super-block, the Embedded Code Generator's block property settings <br />
: window will appear (refer Fig. 3)<br />
: Provide path name and then press OK for code generation (refer Fig. 4)<br />
<br />
[[image:scicoslab3.png]] <br />
::::::: Figure 3 – Embedded Code Generator window<br />
<br />
[[image:scicoslab4.png]] <br />
::::::: Figure 4 – Code Generator results<br />
<br />
Step 4:<br />
* Open MPLAB IDE and import “pic30.cof” file created by the code generator in Step 3.<br />
: Connect the FLEX board (with DEMO2 motion control pack) to ICD for programming the<br />
dsPic (refer Fig. 5). Program the FLEX board but do not start the application.<br />
<br />
[[image:cof_ide1.png]] <br />
[[image:cof_ide2.png]] <br />
::::::: Figure 5 - MPLAB IDE: COF file importing and target programming<br />
<br />
Step 5:<br />
* Check TCP/IP settings of the PC ethernet port (refer Fig. 6).<br />
<br />
[[image:scicoslab6.png]] <br />
::::::: Figure 6 – Check the TCP/IP port settings <br />
<br />
Step 6:<br />
* Open the PC-side file “PCside_AmazingBall_UDP_PIDtuning.cos” in Scicos;<br />
: The .cos file contains the schematic for the PC-side (refer Fig. 7).<br />
: Connect the ethernet cable and start the almost-real-time simulation in SCICOS.<br />
: The application shows the received UDP data on multiple scopes and sends data for PID tuning <br />
: to the FLEX board (refer Fig. 8).<br />
<br />
[[image:scicoslab7.png]] <br />
::::::: Figure 7 – PC-side schematic<br />
<br />
[[image:scicoslab8.png]] <br />
::::::: Figure 8 – PC-side application (PID tuner)<br />
<br />
Step 7:<br />
* Release the reset to run the demo on the board(refer Fig.9);<br />
: Initially the application calibrates the touch screen (refer Fig. 11), then the control algorithm starts.<br />
: The application running on the board must be started after running the SCICOS diagram simulation to allow <br />
: proper initialization of the FLEX UDP interface. If the FLEX board does not receive data from the PC for any reason <br />
: the control algorithm does not start. (refer Fig.12).<br />
<br />
[[image:released_reset.png]]<br />
::::::: Figure 9 - MPLAB IDE: Target released from reset<br />
<br />
[[image:scicoslab10.png]]<br />
::::::: Figure 10 – Touch panel calibration<br />
<br />
[[image:scicoslab11.png]]<br />
::::::: Figure 11 – Control result<br />
<br />
[[image:scicoslab12.png]]<br />
::::::: Figure 12 – Data Plot</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communicationAmazing Ball Control System: An example of PID control and UDP communication2012-08-27T13:00:50Z<p>Erikadds: </p>
<hr />
<div>Step 1:<br />
* Open ScicosLab 4.4b7, the Scicos-FLEX pack is recognized by the program (refer Fig. 1).<br />
: Change the working directory to “C:\Programmi\scilab\scicoslab_44b7\contrib\dspic”.<br />
: Type exec builder.sce to build any application of the pack.<br />
<br />
[[image:scicoslab1.png]]<br />
::::::: Figure 1 – ScicosLab<br />
<br />
Step 2:<br />
* Open file “pid_ctrl_codegen_udp_tuning_square_circle.cos” (refer Fig. 2) in Scicos.<br />
: The .cos file contains the schematic for the FLEX embedded code generation (with SCICOS).<br />
: This application is for tuning coefficients of the PID control for improving system<br />
: performance.<br />
<br />
[[image:scicoslab2.png]]<br />
::::::: Figure 2 – Control system schematic<br />
<br />
Step 3:<br />
* Click menu CodeGen and select FlexCodeGen.<br />
: Click on the super-block, the Embedded Code Generator's block property settings <br />
: window will appear (refer Fig. 3)<br />
: Provide path name and then press OK for code generation (refer Fig. 4)<br />
<br />
[[image:scicoslab3.png]] <br />
::::::: Figure 3 – Embedded Code Generator window<br />
<br />
[[image:scicoslab4.png]] <br />
::::::: Figure 4 – Code Generator results<br />
<br />
Step 4:<br />
* Open MPLAB IDE and import “pic30.cof” file created by the code generator in Step 3.<br />
: Connect the FLEX board (with DEMO2 motion control pack) to ICD for programming the<br />
dsPic (refer Fig. 5). Program the FLEX board but do not start the application.<br />
* [[File:AB_udp_tuning.zip AmazingBall UDP PID-tuning demo]] The AmazingBall sends and receives and you can tune the PID parameters.<br />
* [[Archive:AB_udp.zip AmazingBall-UDP-demo]] The AmazingBall sends only but it doesn't receive UDP data (this is the basic demo for the AmazingBall).<br />
<br />
[[image:cof_ide1.png]] <br />
[[image:cof_ide2.png]] <br />
::::::: Figure 5 - MPLAB IDE: COF file importing and target programming<br />
<br />
Step 5:<br />
* Check TCP/IP settings of the PC ethernet port (refer Fig. 6).<br />
<br />
[[image:scicoslab6.png]] <br />
::::::: Figure 6 – Check the TCP/IP port settings <br />
<br />
Step 6:<br />
* Open the PC-side file “PCside_AmazingBall_UDP_PIDtuning.cos” in Scicos;<br />
: The .cos file contains the schematic for the PC-side (refer Fig. 7).<br />
: Connect the ethernet cable and start the almost-real-time simulation in SCICOS.<br />
: The application shows the received UDP data on multiple scopes and sends data for PID tuning <br />
: to the FLEX board (refer Fig. 8).<br />
<br />
[[image:scicoslab7.png]] <br />
::::::: Figure 7 – PC-side schematic<br />
<br />
[[image:scicoslab8.png]] <br />
::::::: Figure 8 – PC-side application (PID tuner)<br />
<br />
Step 7:<br />
* Release the reset to run the demo on the board(refer Fig.9);<br />
: Initially the application calibrates the touch screen (refer Fig. 11), then the control algorithm starts.<br />
: The application running on the board must be started after running the SCICOS diagram simulation to allow <br />
: proper initialization of the FLEX UDP interface. If the FLEX board does not receive data from the PC for any reason <br />
: the control algorithm does not start. (refer Fig.12).<br />
<br />
[[image:released_reset.png]]<br />
::::::: Figure 9 - MPLAB IDE: Target released from reset<br />
<br />
[[image:scicoslab10.png]]<br />
::::::: Figure 10 – Touch panel calibration<br />
<br />
[[image:scicoslab11.png]]<br />
::::::: Figure 11 – Control result<br />
<br />
[[image:scicoslab12.png]]<br />
::::::: Figure 12 – Data Plot</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communicationAmazing Ball Control System: An example of PID control and UDP communication2012-08-27T12:52:10Z<p>Erikadds: </p>
<hr />
<div>Step 1:<br />
* Open ScicosLab 4.4b7, the Scicos-FLEX pack is recognized by the program (refer Fig. 1).<br />
: Change the working directory to “C:\Programmi\scilab\scicoslab_44b7\contrib\dspic”.<br />
: Type exec builder.sce to build any application of the pack.<br />
<br />
[[image:scicoslab1.png]]<br />
::::::: Figure 1 – ScicosLab<br />
<br />
Step 2:<br />
* Open file “pid_ctrl_codegen_udp_tuning_square_circle.cos” (refer Fig. 2) in Scicos.<br />
: The .cos file contains the schematic for the FLEX embedded code generation (with SCICOS).<br />
: This application is for tuning coefficients of the PID control for improving system<br />
: performance.<br />
<br />
[[image:scicoslab2.png]]<br />
::::::: Figure 2 – Control system schematic<br />
<br />
Step 3:<br />
* Click menu CodeGen and select FlexCodeGen.<br />
: Click on the super-block, the Embedded Code Generator's block property settings <br />
: window will appear (refer Fig. 3)<br />
: Provide path name and then press OK for code generation (refer Fig. 4)<br />
<br />
[[image:scicoslab3.png]] <br />
::::::: Figure 3 – Embedded Code Generator window<br />
<br />
[[image:scicoslab4.png]] <br />
::::::: Figure 4 – Code Generator results<br />
<br />
Step 4:<br />
* Open MPLAB IDE and import “pic30.cof” file created by the code generator in Step 3.<br />
: Connect the FLEX board (with DEMO2 motion control pack) to ICD for programming the<br />
dsPic (refer Fig. 5). Program the FLEX board but do not start the application.<br />
* [[File:AB_udp_tuning.zip AmazingBall UDP PID-tuning demo]] The AmazingBall sends and receives and you can tune the PID parameters.<br />
* [[File:AB_udp.zip AmazingBall UDP demo]] The AmazingBall sends only but it doesn't receive UDP data (this is the basic demo for the AmazingBall).<br />
<br />
[[image:cof_ide1.png]] <br />
[[image:cof_ide2.png]] <br />
::::::: Figure 5 - MPLAB IDE: COF file importing and target programming<br />
<br />
Step 5:<br />
* Check TCP/IP settings of the PC ethernet port (refer Fig. 6).<br />
<br />
[[image:scicoslab6.png]] <br />
::::::: Figure 6 – Check the TCP/IP port settings <br />
<br />
Step 6:<br />
* Open the PC-side file “PCside_AmazingBall_UDP_PIDtuning.cos” in Scicos;<br />
: The .cos file contains the schematic for the PC-side (refer Fig. 7).<br />
: Connect the ethernet cable and start the almost-real-time simulation in SCICOS.<br />
: The application shows the received UDP data on multiple scopes and sends data for PID tuning <br />
: to the FLEX board (refer Fig. 8).<br />
<br />
[[image:scicoslab7.png]] <br />
::::::: Figure 7 – PC-side schematic<br />
<br />
[[image:scicoslab8.png]] <br />
::::::: Figure 8 – PC-side application (PID tuner)<br />
<br />
Step 7:<br />
* Release the reset to run the demo on the board(refer Fig.9);<br />
: Initially the application calibrates the touch screen (refer Fig. 11), then the control algorithm starts.<br />
: The application running on the board must be started after running the SCICOS diagram simulation to allow <br />
: proper initialization of the FLEX UDP interface. If the FLEX board does not receive data from the PC for any reason <br />
: the control algorithm does not start. (refer Fig.12).<br />
<br />
[[image:released_reset.png]]<br />
::::::: Figure 9 - MPLAB IDE: Target released from reset<br />
<br />
[[image:scicoslab10.png]]<br />
::::::: Figure 10 – Touch panel calibration<br />
<br />
[[image:scicoslab11.png]]<br />
::::::: Figure 11 – Control result<br />
<br />
[[image:scicoslab12.png]]<br />
::::::: Figure 12 – Data Plot</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communicationAmazing Ball Control System: An example of PID control and UDP communication2012-08-27T12:51:45Z<p>Erikadds: </p>
<hr />
<div>Step 1:<br />
* Open ScicosLab 4.4b7, the Scicos-FLEX pack is recognized by the program (refer Fig. 1).<br />
: Change the working directory to “C:\Programmi\scilab\scicoslab_44b7\contrib\dspic”.<br />
: Type exec builder.sce to build any application of the pack.<br />
<br />
[[image:scicoslab1.png]]<br />
::::::: Figure 1 – ScicosLab<br />
<br />
Step 2:<br />
* Open file “pid_ctrl_codegen_udp_tuning_square_circle.cos” (refer Fig. 2) in Scicos.<br />
: The .cos file contains the schematic for the FLEX embedded code generation (with SCICOS).<br />
: This application is for tuning coefficients of the PID control for improving system<br />
: performance.<br />
<br />
[[image:scicoslab2.png]]<br />
::::::: Figure 2 – Control system schematic<br />
<br />
Step 3:<br />
* Click menu CodeGen and select FlexCodeGen.<br />
: Click on the super-block, the Embedded Code Generator's block property settings <br />
: window will appear (refer Fig. 3)<br />
: Provide path name and then press OK for code generation (refer Fig. 4)<br />
<br />
[[image:scicoslab3.png]] <br />
::::::: Figure 3 – Embedded Code Generator window<br />
<br />
[[image:scicoslab4.png]] <br />
::::::: Figure 4 – Code Generator results<br />
<br />
Step 4:<br />
* Open MPLAB IDE and import “pic30.cof” file created by the code generator in Step 3.<br />
: Connect the FLEX board (with DEMO2 motion control pack) to ICD for programming the<br />
dsPic (refer Fig. 5). Program the FLEX board but do not start the application.<br />
* [[File:AB_udp.zip AmazingBall UDP PID-tuning demo]] The AmazingBall sends and receives and you can tune the PID parameters.<br />
* [[File:AB_udp.zip AmazingBall UDP demo]] The AmazingBall sends only but it doesn't receive UDP data (this is the basic demo for the AmazingBall).<br />
<br />
[[image:cof_ide1.png]] <br />
[[image:cof_ide2.png]] <br />
::::::: Figure 5 - MPLAB IDE: COF file importing and target programming<br />
<br />
Step 5:<br />
* Check TCP/IP settings of the PC ethernet port (refer Fig. 6).<br />
<br />
[[image:scicoslab6.png]] <br />
::::::: Figure 6 – Check the TCP/IP port settings <br />
<br />
Step 6:<br />
* Open the PC-side file “PCside_AmazingBall_UDP_PIDtuning.cos” in Scicos;<br />
: The .cos file contains the schematic for the PC-side (refer Fig. 7).<br />
: Connect the ethernet cable and start the almost-real-time simulation in SCICOS.<br />
: The application shows the received UDP data on multiple scopes and sends data for PID tuning <br />
: to the FLEX board (refer Fig. 8).<br />
<br />
[[image:scicoslab7.png]] <br />
::::::: Figure 7 – PC-side schematic<br />
<br />
[[image:scicoslab8.png]] <br />
::::::: Figure 8 – PC-side application (PID tuner)<br />
<br />
Step 7:<br />
* Release the reset to run the demo on the board(refer Fig.9);<br />
: Initially the application calibrates the touch screen (refer Fig. 11), then the control algorithm starts.<br />
: The application running on the board must be started after running the SCICOS diagram simulation to allow <br />
: proper initialization of the FLEX UDP interface. If the FLEX board does not receive data from the PC for any reason <br />
: the control algorithm does not start. (refer Fig.12).<br />
<br />
[[image:released_reset.png]]<br />
::::::: Figure 9 - MPLAB IDE: Target released from reset<br />
<br />
[[image:scicoslab10.png]]<br />
::::::: Figure 10 – Touch panel calibration<br />
<br />
[[image:scicoslab11.png]]<br />
::::::: Figure 11 – Control result<br />
<br />
[[image:scicoslab12.png]]<br />
::::::: Figure 12 – Data Plot</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_example_of_PID_control_and_UDP_communicationAmazing Ball Control System: An example of PID control and UDP communication2012-05-10T08:04:23Z<p>Erikadds: </p>
<hr />
<div>Step 1:<br />
* Open ScicosLab 4.4b7, the Scicos-FLEX pack is recognized by the program (refer Fig. 1).<br />
: Change the working directory to “C:\Programmi\scilab\scicoslab_44b7\contrib\dspic”.<br />
: Type exec builder.sce to build any application of the pack.<br />
<br />
[[image:scicoslab1.png]]<br />
::::::: Figure 1 – ScicosLab<br />
<br />
Step 2:<br />
* Open file “pid_ctrl_codegen_udp_tuning_square_circle.cos” (refer Fig. 2) in Scicos.<br />
: The .cos file contains the schematic for the FLEX embedded code generation (with SCICOS).<br />
: This application is for tuning coefficients of the PID control for improving system<br />
: performance.<br />
<br />
[[image:scicoslab2.png]]<br />
::::::: Figure 2 – Control system schematic<br />
<br />
Step 3:<br />
* Click menu CodeGen and select FlexCodeGen.<br />
: Click on the super-block, the Embedded Code Generator's block property settings <br />
: window will appear (refer Fig. 3)<br />
: Provide path name and then press OK for code generation (refer Fig. 4)<br />
<br />
[[image:scicoslab3.png]] <br />
::::::: Figure 3 – Embedded Code Generator window<br />
<br />
[[image:scicoslab4.png]] <br />
::::::: Figure 4 – Code Generator results<br />
<br />
Step 4:<br />
* Open MPLAB IDE and import “pic30.cof” file created by the code generator in Step 3.<br />
: Connect the FLEX board (with DEMO2 motion control pack) to ICD for programming the<br />
dsPic (refer Fig. 5). Program the FLEX board but do not start the application.<br />
<br />
[[image:cof_ide1.png]] <br />
[[image:cof_ide2.png]] <br />
::::::: Figure 5 - MPLAB IDE: COF file importing and target programming<br />
<br />
Step 5:<br />
* Check TCP/IP settings of the PC ethernet port (refer Fig. 6).<br />
<br />
[[image:scicoslab6.png]] <br />
::::::: Figure 6 – Check the TCP/IP port settings <br />
<br />
Step 6:<br />
* Open the PC-side file “PCside_AmazingBall_UDP_PIDtuning.cos” in Scicos;<br />
: The .cos file contains the schematic for the PC-side (refer Fig. 7).<br />
: Connect the ethernet cable and start the almost-real-time simulation in SCICOS.<br />
: The application shows the received UDP data on multiple scopes and sends data for PID tuning <br />
: to the FLEX board (refer Fig. 8).<br />
<br />
[[image:scicoslab7.png]] <br />
::::::: Figure 7 – PC-side schematic<br />
<br />
[[image:scicoslab8.png]] <br />
::::::: Figure 8 – PC-side application (PID tuner)<br />
<br />
Step 7:<br />
* Release the reset to run the demo on the board(refer Fig.9);<br />
: Initially the application calibrates the touch screen (refer Fig. 11), then the control algorithm starts.<br />
: The application running on the board must be started after running the SCICOS diagram simulation to allow <br />
: proper initialization of the FLEX UDP interface. If the FLEX board does not receive data from the PC for any reason <br />
: the control algorithm does not start. (refer Fig.12).<br />
<br />
[[image:released_reset.png]]<br />
::::::: Figure 9 - MPLAB IDE: Target released from reset<br />
<br />
[[image:scicoslab10.png]]<br />
::::::: Figure 10 – Touch panel calibration<br />
<br />
[[image:scicoslab11.png]]<br />
::::::: Figure 11 – Control result<br />
<br />
[[image:scicoslab12.png]]<br />
::::::: Figure 12 – Data Plot</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=FLEX_Multibus_Daughter_BoardFLEX Multibus Daughter Board2012-04-26T08:19:18Z<p>Erikadds: /* FAQ */</p>
<hr />
<div>= Description =<br />
The FLEX Multibus Board is a FLEX Daughter Board, targeted specifically for data communication.<br />
The Multibus Board simplifies the work with the communication peripherals integrated in the Microchip dsPIC (R) DSC. The board, which is fully modular, provides a set of modules that realize the hardware interface with the buses. The Multibus Base Daughter Board is piggybacked on FLEX Full/Light Base Board.<br />
<br />
The following slots are available on the Multibus Board:<br />
<br />
* UART2 slot, for Serial TTL/RS232/RS485/RS422 module<br />
* UART1 slot, for Serial TTL/RS232/RS485 module<br />
* CAN1 slot, for CAN module<br />
* CAN2 slot, for CAN module<br />
* I2C slot (channel selectable), for I2C module<br />
* SPI slot (channel selectable), for SPI module<br />
* Ethernet slot, for 10Mbit Ethernet module<br />
<br />
Modules are mounted only if needed. For example, if the application requires the Ethernet interface and the connection to the CAN bus, only the corresponding modules will be mounted on the Multibus Board, leaving the remaining pins free for other use.<br />
<br />
[http://www.evidence.eu.com/content/view/168/211/ FLEX Multibus Daughter Board product page]<br />
<br />
<br />
= FAQ =<br />
* '''Could you please explain how to create a project based on the Microchip UDP (or TCP/IP) stack?'''<br />
<br />
If you use the Demo2 pack for motion control (Motion Daughter Board) you can create a project starting from Scicos.<br />
With the Multibus daughter board you can implement the Microchip TCP/IP stack in a project in this way.<br />
<br />
In RT-DRUID/Eclipse, create a project using the template 'pic30/FLEX Multibus board/UDP demo'. <br />
<br />
This is the link to the example folder in the repository:<br />
[http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/pic30/pic30_MultibusBoard_udp_demo/ UDP demo]<br />
<br />
Description of the files:<br />
:"HardwareProfile.h" contains the HW configuration macros for the Multibus board.<br />
:"TCPIPConfig.h" contains the IP address used by the net protocols.<br />
:"flex_udp.c" and "flex_udp.h" contain the functions you can use in your UDP application.<br />
:"code.c" and "conf.oil" are the application files. <br />
<br />
The image below shows how to set the jumpers and the Ethernet module on the daughter board.<br />
<br />
:[[image:multibus_eth.PNG|300px]]<br />
<br />
:<br />
:<br />
* '''Could you please explain how to use RS232 module with the FLEX Multibus daugther board?'''<br />
You just have to mount the RS232 module on the socket and to set up two jumpers as shown in the following<br />
image.<br />
<br />
:[[image:rs232_multibus.PNG|300px]]<br />
<br />
:<br />
:<br />
* '''Could you please explain how to set up the basic demo-project based on CAN bus?'''<br />
<br />
Prerequisites HW: Multibus and FLEX boards with CAN modules.<br />
Prerequisites SW: RT-DRUID and Erika Enterprise v1.6.0.<br />
<br />
The Erika demo-project based on CAN bus can be found in the RT-Druid C/C++ templates.<br />
<br />
Description of the files:<br />
:"conf.oil" is the main configuration file. You can uncomment the line you need, to configure the device as a sender or receiver.<br />
:"conf_sender.oil" is the CAN sender configuration file.<br />
:"conf_receiver.oil" is the CAN receiver configuration file.<br />
:"code_sender.c" and "code_receiver.c" are the application source files<br />
<br />
The image below shows how to connect the boards and set the jumpers on the CAN modules. <br />
<br />
:[[image:can_multibus.PNG|300px]]<br />
<br />
:<br />
:</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=How_to_use_Scicos-FLEX_on_non-FLEX_boardsHow to use Scicos-FLEX on non-FLEX boards2012-04-10T09:28:43Z<p>Erikadds: </p>
<hr />
<div>It is possible to use Scicos-FLEX with non-FLEX boards.<br />
These steps should make it possible to compile an EE application based on a custom board.<br />
<br />
Here is what you need to do:<br />
<br />
* You need to write your own blocks. see the following link<br />
** [[How to add a new Scicos block to ERIKA Enterprise]]<br />
* You need to create a template for your board.<br />
** First, start from an existing template. The reference template is stored into the example eclipse plugin. under my PC, it is currently <tt>C:\Evidence\eclipse\plugins\com.eu.evidence.ee.templates.dspic_1.5.1.201011221106\examples\pic30\pic30_scicos</tt><br />
** Then, copy the template in another directory under the examples directory (for example, ".../examples/pic30/myboard")<br />
** change, in the <tt>template.xml</tt>, the board ID from "board_flex" to "myboard"<br />
** change the code to reflect your board configuration by editing the 'oil' and the source files. <br />
* Now you need to add the template in the Scicos target settings, by editing the file SCI+'/contrib/scicos_ee/scicos_flex/dsPIC/macros /codegen/SetTarget_.sci', changing the templates list as follows: <tt>lab_template = ['board_flex', 'board_easylab', 'myboard'];</tt><br />
* At this point you need to recompile all the files by running "builder.sce". <br />
<br />
Finally, when generating the code, use "myboard" instead of "board_flex" in the Target board parameter in the code generator dialog box.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Scicos_BlocksScicos Blocks2012-03-16T09:53:31Z<p>Erikadds: </p>
<hr />
<div>= Introduction =<br />
<br />
Here a basilar description of scicos blocks for FLEX and Easylab boards. Each of these blocks has a more complete description integrated with scicos help feature. To acces to them just right click on a block and select help from contextual menu.<br />
<br />
= Code generation general purpose palettes =<br />
<br />
These are the palettes for code generation that do not depend on target board (for further info open the Scicos Help feature)<br />
<br />
* MCHP16 Sources<br />
* MCHP16 Sinks<br />
* MCHP16 Linear<br />
* MCHP16 Non Linear<br />
* MCHP16 Logic<br />
* MCHP16 Branching<br />
* MCHP16 Typeconversion<br />
<br />
= FLEX & Daughter boards palettes =<br />
<br />
This is a short description of the palettes available on the Scicos Pack for FLEX and her daughter boards (for further info open the Scicos Help feature).<br />
<br />
* FLEX-DemoBoard<br />
* FLEX-MotionBoard<br />
* FLEX<br />
* FLEX-Communication<br />
<br />
= RT Data Exchange Palette =<br />
<br />
Palette with all the blocks to perform communication between a PC simulation and the target boards <br />
(NOT FOR CODE GENERATION) (for further info open the Scicos Help feature)<br />
<br />
* RT Data Exchange<br />
<br />
= Amazing Ball palette =<br />
<br />
This is a short description of the blocks available for the AMAZING BALL system (for further info open the Scicos Help feature)<br />
* Amazing Ball<br />
<br />
= Easylab board palette =<br />
<br />
This is a short description of the blocks available for the EASYLAB board (for further info open the Scicos Help feature)<br />
* Easylab<br />
<br />
= Miscellaneous palette =<br />
<br />
This palette contains general purpose blocks available for AMAZING BALL, FLEX and EASYLAB (for further info open the Scicos Help feature)<br />
* Miscellaneous blocks (SPRINTF)<br />
Note: To compile this block a recent version of the Microchip compiler is needed. Recommended versions: v3.30, v3.31 or later. Please do not use v3.25! <br />
<br />
= SMCube palette =<br />
<br />
This palette contains blocks for FSM-based applications (for further info open the Scicos Help feature)<br />
* SMCube blocks (SMCUBE)<br />
Note: To compile this block a recent version of the Microchip compiler is needed. Recommended versions: v3.30, v3.31 or later. Please do not use v3.25!</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Scicos_BlocksScicos Blocks2012-03-09T08:37:36Z<p>Erikadds: </p>
<hr />
<div>= Introduction =<br />
<br />
Here a basilar description of scicos blocks for FLEX and Easylab boards. Each of these blocks has a more complete description integrated with scicos help feature. To acces to them just right click on a block and select help from contextual menu.<br />
<br />
= Code generation general purpose palettes =<br />
<br />
These are the palettes for code generation that do not depend on target board (for further info open the Scicos Help feature)<br />
<br />
* [[MCHP16 Sources]]<br />
* [[MCHP16 Sinks]]<br />
* [[MCHP16 Linear]]<br />
* [[MCHP16 Non Linear]]<br />
* [[MCHP16 Logic]]<br />
* [[MCHP16 Branching]]<br />
* [[MCHP16 Typeconversion]]<br />
<br />
= FLEX & Daughter boards palettes =<br />
<br />
This is a short description of the palettes available on the Scicos Pack for FLEX and her daughter boards (for further info open the Scicos Help feature).<br />
<br />
* [[FLEX-DemoBoard]]<br />
* [[FLEX-MotionBoard]]<br />
* [[FLEX]]<br />
* [[FLEX-Communication]]<br />
<br />
= RT Data Exchange Palette =<br />
<br />
Palette with all the blocks to perform communication between a PC simulation and the target boards <br />
(NOT FOR CODE GENERATION) (for further info open the Scicos Help feature)<br />
<br />
* [[RT Data Exchange]]<br />
<br />
= Amazing Ball palette =<br />
<br />
This is a short description of the blocks available for the AMAZING BALL system (for further info open the Scicos Help feature)<br />
* [[Amazing Ball]]<br />
<br />
= Easylab board palette =<br />
<br />
This is a short description of the blocks available for the EASYLAB board (for further info open the Scicos Help feature)<br />
* [[Easylab]]<br />
<br />
= Miscellaneous palette =<br />
<br />
This palette contains general purpose blocks available for AMAZING BALL, FLEX and EASYLAB (for further info open the Scicos Help feature)<br />
* Miscellaneous blocks (SPRINTF)<br />
Note: To compile this block a recent version of the Microchip compiler is needed. Recommended versions: v3.30, v3.31 or later. Please do not use v3.25! <br />
<br />
= SMCube palette =<br />
<br />
This palette contains blocks for FSM-based applications (for further info open the Scicos Help feature)<br />
* SMCube blocks (SMCUBE)<br />
Note: To compile this block a recent version of the Microchip compiler is needed. Recommended versions: v3.30, v3.31 or later. Please do not use v3.25!</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Scicos_BlocksScicos Blocks2012-02-10T16:44:21Z<p>Erikadds: </p>
<hr />
<div>= Introduction =<br />
<br />
Here a basilar description of scicos blocks for FLEX and Easylab boards. Each of these blocks has a more complete description integrated with scicos help feature. To acces to them just right click on a block and select help from contextual menu.<br />
<br />
= Code generation general purpose palettes =<br />
<br />
These are the palettes for code generation that do not depend on target board (for further info open the Scicos Help feature)<br />
<br />
* [[MCHP16 Sources]]<br />
* [[MCHP16 Sinks]]<br />
* [[MCHP16 Linear]]<br />
* [[MCHP16 Non Linear]]<br />
* [[MCHP16 Logic]]<br />
* [[MCHP16 Branching]]<br />
* [[MCHP16 Typeconversion]]<br />
<br />
= FLEX & Daughter boards palettes =<br />
<br />
This is a short description of the palettes available on the Scicos Pack for FLEX and her daughter boards (for further info open the Scicos Help feature).<br />
<br />
* [[FLEX-DemoBoard]]<br />
* [[FLEX-MotionBoard]]<br />
* [[FLEX]]<br />
* [[FLEX-Communication]]<br />
<br />
= RT Data Exchange Palette =<br />
<br />
Palette with all the blocks to perform communication between a PC simulation and the target boards <br />
(NOT FOR CODE GENERATION) (for further info open the Scicos Help feature)<br />
<br />
* [[RT Data Exchange]]<br />
<br />
= Amazing Ball palette =<br />
<br />
This is a short description of the blocks available for the AMAZING BALL system (for further info open the Scicos Help feature)<br />
* [[Amazing Ball]]<br />
<br />
= Easylab board palette =<br />
<br />
This is a short description of the blocks available for the EASYLAB board (for further info open the Scicos Help feature)<br />
* [[Easylab]]<br />
<br />
= Miscellaneous palette =<br />
<br />
This palette contains general purpose blocks available for AMAZING BALL, FLEX and EASYLAB (for further info open the Scicos Help feature)<br />
* Miscellaneous blocks (SPRINTF)<br />
<br />
= SMCube palette =<br />
<br />
This palette contains blocks for FSM-based applications (for further info open the Scicos Help feature)<br />
* SMCube blocks (SMCUBE)</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Scicos_BlocksScicos Blocks2012-02-10T16:37:56Z<p>Erikadds: </p>
<hr />
<div>= Introduction =<br />
<br />
Here a basilar description of scicos blocks for FLEX and Easylab boards. Each of these blocks has a more complete description integrated with scicos help feature. To acces to them just right click on a block and select help from contextual menu.<br />
<br />
= Code generation general purpose palettes =<br />
<br />
These are the palettes for code generation that do not depend on target board <br />
<br />
* [[MCHP16 Sources]]<br />
* [[MCHP16 Sinks]]<br />
* [[MCHP16 Linear]]<br />
* [[MCHP16 Non Linear]]<br />
* [[MCHP16 Logic]]<br />
* [[MCHP16 Branching]]<br />
* [[MCHP16 Typeconversion]]<br />
<br />
= FLEX & Daughter boards palettes =<br />
<br />
This is a short description of the palettes available on the Scicos Pack for FLEX and her daughter boards.<br />
<br />
* [[FLEX-DemoBoard]]<br />
* [[FLEX-MotionBoard]]<br />
* [[FLEX]]<br />
* [[FLEX-Communication]]<br />
<br />
= RT Data Exchange Palette =<br />
<br />
Palette with all the blocks to perform communication between a PC simulation and the target boards <br />
(Hardware-in-the-loop approach)<br />
<br />
* [[RT Data Exchange]]<br />
<br />
= Amazing Ball palette =<br />
* [[Amazing Ball]]<br />
<br />
= Easylab board palette =<br />
<br />
* [[Easylab]]<br />
<br />
= Miscellaneous palette =<br />
<br />
* Miscellaneous blocks (SPRINTF)<br />
<br />
= SMCube palette =<br />
<br />
* SMCube blocks (SMCUBE)</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Scicos_BlocksScicos Blocks2012-02-10T16:34:19Z<p>Erikadds: /* FLEX & Daughter boards palettes */</p>
<hr />
<div>= Introduction =<br />
<br />
Here a basilar description of scicos blocks for FLEX and Easylab boards. Each of these blocks has a more complete description integrated with scicos help feature. To acces to them just right click on a block and select help from contextual menu.<br />
<br />
= Code generation general purpose palettes =<br />
<br />
These are the palettes for code generation that do not depend on target board <br />
<br />
* [[MCHP16 Sources]]<br />
* [[MCHP16 Sinks]]<br />
* [[MCHP16 Linear]]<br />
* [[MCHP16 Non Linear]]<br />
* [[MCHP16 Logic]]<br />
* [[MCHP16 Branching]]<br />
* [[MCHP16 Typeconversion]]<br />
<br />
= FLEX & Daughter boards palettes =<br />
<br />
This is a short description of the palettes available on the Scicos Pack for FLEX and her daughter boards.<br />
<br />
* [[FLEX-DemoBoard]]<br />
* [[FLEX-MotionBoard]]<br />
* [[FLEX]]<br />
* [[FLEX-Communication]]<br />
<br />
= RT Data Exchange Palette =<br />
<br />
Palette with all the blocks to perform communication between a PC simulation and the target boards <br />
(Hardware-in-the-loop approach)<br />
<br />
* [[RT Data Exchange]]<br />
<br />
= Amazing Ball palette =<br />
* [[Amazing Ball]]<br />
<br />
= Easylab board palette =<br />
<br />
* [[Easylab]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_8.JPGFile:Amazing 8.JPG2012-01-24T15:11:50Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_7.JPGFile:Amazing 7.JPG2012-01-24T15:11:33Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_6.JPGFile:Amazing 6.JPG2012-01-24T15:11:20Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_5.JPGFile:Amazing 5.JPG2012-01-24T15:11:07Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_4.JPGFile:Amazing 4.JPG2012-01-24T15:10:54Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_3.JPGFile:Amazing 3.JPG2012-01-24T15:10:38Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Amazing_2.JPGFile:Amazing 2.JPG2012-01-24T15:10:24Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Unpacking_the_Amazing_ball_packageUnpacking the Amazing ball package2012-01-24T15:10:13Z<p>Erikadds: </p>
<hr />
<div>This page shows the steps needed to unpack and mount the Amazing Ball.<br />
<br />
You should have received the package containing the Amazing Ball mechanical parts and hardware.<br />
Please open the lateral side to let the mechanical part and the electrobix be removed easily as shown below<br />
<br />
[[Image:Amazing_2.JPG]]<br />
<br />
Remove the coverage from the touch panel to simplify the extraction of the parts.<br />
<br />
[[Image:Amazing_3.JPG]]<br />
<br />
Inside the box, you will find a carton package similar to the typical Flex box, but with an "Amazing Ball" sticker on it.<br />
<br />
[[Image:Amazing_4.JPG]]<br />
<br />
...Open it, and you will find the electronic (already mounted), plus the iron ball.<br />
<br />
[[Image:Amazing_5.JPG]]<br />
<br />
Once opened, you should unscrew the four white plastic screws on the right of the picture below, and then fix the electronic on the holes on the bottom metal plate. The holes are of a size the fits either the FLEX Light or the FLEX Full.<br />
<br />
[[Image:Amazing_6.JPG]]<br />
<br />
Once the electronic is fixed to the metal plate, you should fix the connectors of the servo motors and of the touchscreen. Please note the numbers on each connector, as well as the colors of the cables in the picture below<br />
<br />
[[Image:Amazing_7.JPG]]<br />
<br />
Once done that, you should have the Amazing Ball mounted in a way similar to the following picture. (Please note that the power connector is not included in the package)<br />
<br />
[[Image:Amazing_8.JPG]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Ab_foto.pngFile:Ab foto.png2012-01-24T14:03:55Z<p>Erikadds: uploaded a new version of &quot;File:Ab foto.png&quot;</p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Ab_foto.pngFile:Ab foto.png2012-01-24T14:02:28Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_IntroductionAmazing Ball Introduction2012-01-24T14:01:53Z<p>Erikadds: </p>
<hr />
<div>The '''Amazing Ball System''':<br />
<br /><br /><br />
<br />
{| class="wikitable"<br />
| [[image:ab_foto.png]]<br />
|-<br />
| This section describes the Amazing Ball, a ball-on-plate balancing system. The realization of the system was obtained with the simultaneous consideration towards constraints like cost, performance, functionality, extendibility, and educational merit.<br />
A complete system description for the ball-on-plate system is presented.<br />
<br />
PHYSICAL SYSTEM DESCRIPTION<br />
<br />
The physical system consists of an mechanical plate, two actuation mechanisms for tilting the plate about two axes, a ball position sensor, instrumentation for<br />
signal processing, and real-time control software/hardware. The entire system is mounted on a mechanical (steel) base plate and is supported by four vertical springs and a central joint. <br />
<br />
The motors are operated in angular position mode for ease of modeling and controls. A pulse-width modulated signal is employed for this purpose. The servos are powered by a 6V DC power supply.<br />
<br />
A resistive touch sensitive glass screen (hantouch.com) that is actually meant to be a computer touchscreen was used for sensing the ball position. It provides an extremely reliable, accurate, and economical solution to the ball position sensing problem. The screen consists of three layers: a glass sheet, a conductive coating on<br />
the glass sheet, and a hard-coated conductive topsheet.<br />
An external DC voltage is applied to the four corners of the glass layer. Electrodes spread out the voltage on the glass layer creating a uniform<br />
voltage field. When the top layer is pressed by the weight the ball, the top sheet gets compressed into contact with the conductive coating on the glass layer. As a result, current is drawn from each side of the glass layer in proportion to the distance of the touch from the edge. This generates a set of four voltages at the corners of the glass-sheet. These four voltages are filtered and subsequently<br />
used for computing the ball position coordinates using simple linear relationships. The response time of this sensor is 8-15 ms which is fast enough for this application. The ball rolls on this touch-screen, which in turn is mounted on the<br />
plate.<br />
<br />
The system can be used as an excellent test-bed for testing various control schemes. An optimal controller using full-state feedback can be designed to achieve yet better performance. Although controllers based on the linear model perform extremely well, it will interesting to apply the principles of non-linear controls and seek any further improvements in the system performance.<br />
<br />
The system is distributed with a pre-loaded PID control system for an easier approach.<br />
<br />
A brief guide to unpack the Amazing Ball system package:<br />
* [[Unpacking the Amazing ball package]]<br />
<br />
The following tutorials show how to tune the control algorithm of the Amazing Ball system:<br />
* [[Amazing Ball Control System: An application with the FLEX FULL Motion board and the Scilab/Scicos code generator]]<br />
* [[Amazing Ball Control System: An example of PID control and UDP communication]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_IntroductionAmazing Ball Introduction2012-01-24T13:51:02Z<p>Erikadds: </p>
<hr />
<div>The '''Amazing Ball System''':<br />
<br /><br /><br />
<br />
{| class="wikitable"<br />
| [[image:scicoslab11.png]]<br />
|-<br />
| This section describes the Amazing Ball, a ball-on-plate balancing system. The realization of the system was obtained with the simultaneous consideration towards constraints like cost, performance, functionality, extendibility, and educational merit.<br />
A complete system description for the ball-on-plate system is presented.<br />
<br />
PHYSICAL SYSTEM DESCRIPTION<br />
<br />
The physical system consists of an mechanical plate, two actuation mechanisms for tilting the plate about two axes, a ball position sensor, instrumentation for<br />
signal processing, and real-time control software/hardware. The entire system is mounted on a mechanical (steel) base plate and is supported by four vertical springs and a central joint. <br />
<br />
The motors are operated in angular position mode for ease of modeling and controls. A pulse-width modulated signal is employed for this purpose. The servos are powered by a 6V DC power supply.<br />
<br />
A resistive touch sensitive glass screen (hantouch.com) that is actually meant to be a computer touchscreen was used for sensing the ball position. It provides an extremely reliable, accurate, and economical solution to the ball position sensing problem. The screen consists of three layers: a glass sheet, a conductive coating on<br />
the glass sheet, and a hard-coated conductive topsheet.<br />
An external DC voltage is applied to the four corners of the glass layer. Electrodes spread out the voltage on the glass layer creating a uniform<br />
voltage field. When the top layer is pressed by the weight the ball, the top sheet gets compressed into contact with the conductive coating on the glass layer. As a result, current is drawn from each side of the glass layer in proportion to the distance of the touch from the edge. This generates a set of four voltages at the corners of the glass-sheet. These four voltages are filtered and subsequently<br />
used for computing the ball position coordinates using simple linear relationships. The response time of this sensor is 8-15 ms which is fast enough for this application. The ball rolls on this touch-screen, which in turn is mounted on the<br />
plate.<br />
<br />
The system can be used as an excellent test-bed for testing various control schemes. An optimal controller using full-state feedback can be designed to achieve yet better performance. Although controllers based on the linear model perform extremely well, it will interesting to apply the principles of non-linear controls and seek any further improvements in the system performance.<br />
<br />
The system is distributed with a pre-loaded PID control system for an easier approach.<br />
<br />
A brief guide to unpack the Amazing Ball system package:<br />
* [[Unpacking the Amazing ball package]]<br />
<br />
The following tutorials show how to tune the control algorithm of the Amazing Ball system:<br />
* [[Amazing Ball Control System: An application with the FLEX FULL Motion board and the Scilab/Scicos code generator]]<br />
* [[Amazing Ball Control System: An example of PID control and UDP communication]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Amazing_Ball_Control_System:_An_application_with_the_FLEX_FULL_Motion_board_and_the_Scilab/Scicos_code_generatorAmazing Ball Control System: An application with the FLEX FULL Motion board and the Scilab/Scicos code generator2012-01-24T13:49:54Z<p>Erikadds: </p>
<hr />
<div>= Amazing Ball Control Application =<br />
<br />
'''AMAZING BALL: An example of PID control and USB-UDP communication with the FLEX Motion Daughter Board'''<br />
<br /><br /><br />
<br />
{| class="wikitable"<br />
<br />
Step 1:<br />
* Open Scilab 4.1.2, the Scicos-FLEX pack is recognized by Scilab (refer Fig. 1).<br />
: Change the working directory to “C:\Programmi\scilab-4.1.2\contrib\dspic”.<br />
: Type exec builder.sce to build any application of the pack.<br />
<br />
[[image:scilab.png]]<br />
::::::: Figure 1 – Scilab<br />
<br />
Step 2:<br />
* Open file “pid_ctrl_codegen_usbudp_tuning_square_circle.cos” (refer Fig. 2) in <br />
: Scicos.<br />
: The .cos file contains the schematic for the generation (with SCICOS) of the FLEX <br />
: FULL board program.<br />
: This application is for tuning coefficients of the PID control for improving <br />
: system performance. <br />
<br />
[[image:flexside_schematic.png]]<br />
::::::: Figure 2 – Control system schematic<br />
<br />
Step 3:<br />
* Click menu CodeGen and select FlexCodeGen.<br />
: Click on the super-block, the Embedded Code Generator's block property settings <br />
: window will appear (refer Fig. 3)<br />
: Provide path name and then press OK for code generation (refer Fig. 4)<br />
<br />
[[image:generator_window.png]] <br />
::::::: Figure 3 – Embedded Code Generator window<br />
<br />
[[image:generator_results.png]] <br />
::::::: Figure 4 – Code Generator results<br />
<br />
Step 4:<br />
* Open MPLAB IDE and import “pic30.cof” file created by the code generator in Step 3.<br />
: Connect the FLEX003 (FLEX Full Base Board) to ICD for programming the dsPic <br />
:(refer Fig. 5). The board is programmed and set in reset mode.<br />
<br />
[[image:cof_ide1.png]] <br />
[[image:cof_ide2.png]] <br />
::::::: Figure 5 - MPLAB IDE: COF file importing and target programming<br />
<br />
Step 5:<br />
* Check the USB device recognition in the peripherals window (refer Fig. 6) and <br />
: execute the program app_flex_scicos.exe (refer Fig. 7)<br />
: Note1: The program needs CygWin Win32 usb library and is compiled using make <br />
: command.<br />
: Note2: Download the FLEX USB drivers for Windows and the PIC18 firmware at: <br />
: [[FLEX usb data communication using Scilab and Scicos]] <br />
<br />
[[image:usb_recognition.png]] <br />
::::::: Figure 6 – Check the USB device recognition<br />
<br />
[[image:compilation_gateway.png]] <br />
::::::: Figure 7 – Compilation and start of the program<br />
<br />
Step 6:<br />
* Open the PC-side file “pc_pid_tuning.cos” in Scicos;<br />
: The .cos file contains the schematic for the PC-side (refer Fig. 8). <br />
: The almost-real-time simulation runs in SCICOS environment. The application <br />
: shows the received USB data on the multiple scope and sends other data to the <br />
: FLEX FULL board (refer Fig. 9). <br />
<br />
[[image:pcside_schematic.png]] <br />
::::::: Figure 8 – PC-side schematic<br />
<br />
[[image:pc_side_tuner.png]] <br />
::::::: Figure 9 – PC-side application (PID tuner)<br />
<br />
Step 7:<br />
* Release the reset to run the demo (refer Fig.10);<br />
: Initially the application calibrates the touch screen (refer Fig. 11), followed <br />
: by rest of the demo (refer Fig.12). <br />
<br />
[[image:released_reset.png]]<br />
::::::: Figure 10 - MPLAB IDE: Target released from reset<br />
<br />
[[image:scicoslab10.png]]<br />
::::::: Figure 11 – Touch panel calibration<br />
<br />
[[image:scicoslab11.png]]<br />
::::::: Figure 12 – Control result</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Building_a_Mico32_platform_for_FPG-EYETutorial: Building a Mico32 platform for FPG-EYE2012-01-12T14:13:31Z<p>Erikadds: /* Introduction */</p>
<hr />
<div>= Introduction =<br />
This page explains how to build a configuration file for FPG-EYE's fpga from a source platform with binary camera. <br />
Prerequisites:<br />
* [[Installation of Mico32/FPG-EYE development environment | Install Mico32/FPG-EYE development environment]] <br />
* Get a local copy of Erika repository to have the platform projects.<br />
For further info see this page:[[ERIKA_Enterprise_and_RT-Druid_SVN_Access#Anonymous.2C_readonly_access | ERIKA Enterprise and RT-Druid SVN Access instructions]].<br />
* To download the platform JEDEC file, you need a '''programming cable''' connected to the JTAG port of the board, follow the instructions on [http://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_board How programming the FPG-EYE board].<br />
<br />
= Import platform project in LatticeMico System IDE =<br />
<br />
Launch [http://www.latticesemi.com/products/designsoftware/micodevelopmenttools/index.cfm ''LatticeMico System''] software, and click on '''MSB Perspective''' button (as the following figure):<br />
<br />
[[File:select_msb_from_msb_ide.png|center|thumb|700px| '''MSB''' button]]<br />
<br />
Open the '''Open Platform form''' by selecting the '''File->Open Platform''' menu item:<br />
<br />
[[File:open_msb_from_msb_ide.png|center|thumb|700px| Open '''MSB''' platform]]<br />
<br />
Click the '''Browse''' button and load '''ee/trunk/ee/examples/mico32/demo/platforms/fpg_eye_mico32/msb/soc/fpg_eye_mico32.msb''' file inside Erika repository local copy:<br />
<br />
[[File:Select_fpg_eye_mico32_msb_from_msb_ide.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'']]<br />
<br />
The platform's architecture is visible under '''Sources in Project''' window:<br />
<br />
[[File:fpg_eya_mico32_from_msb.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'' platform architecture]]<br />
<br />
Note: You don't need to make any changes to the platform.<br />
And finally, generate the platform source by selecting the '''Run Generator''' menu item:<br />
<br />
[[File:fpg_eya_mico32_from_msb_run.png|center|thumb|700px| Clicking on '''Run Generator''' we have the platform source]]<br />
<br />
The [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm mico32] platform's Verilog source is generated. To use this platform in FPG-EYE, the source code must be compiled in binary format.<br />
The next session explains how to compile the [http://www.verilog.com/ Verilog] platform's code with ispLEVER tool.<br />
<br />
= Import hardware platform project in ispLever IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLEVER] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_ispLever_ide.png|center|thumb|700px| ''Open project'' from ispLever]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/isplever/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_ispLever.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active.png|center|thumb|700px| ''ispLever'' project structure]]<br />
<br />
Before compiling the ispLever project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the ispLever ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the ispLever the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:camera_component_ngo_in ispLever.png|center|thumb|700px| ''camera_component_mod.ngo'' in ispLever project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the ispLEVER ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:isp_lever_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in ispLever project directory]]<br />
<br />
== Build the platform with ispLEVER ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Force''' :<br />
<br />
[[File:isp_lever_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_isplever.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Import hardware platform project in Diamond IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/diamond Diamond] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_diamond_ide.png|center|thumb|700px| ''Open project'' from Diamond]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/diamond/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_diamond.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active_diamond.png|center|thumb|700px| ''Diamond'' project structure]]<br />
<br />
Before compiling the Diamond project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the Diamond ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the Diamond the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:camera_component_ngo_in_diamond.png|center|thumb|700px| ''camera_component_mod.ngo'' in Diamond project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the Diamond ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:diamond_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in Diamond project directory]]<br />
<br />
== Build the platform with Diamond ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Return All''' :<br />
<br />
[[File:diamond_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_diamond.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Programming the platform on FPG-EYE board =<br />
The last step is download the '''JEDEC''' file into ''FPG-EYE''. Please follow the [[Programming the FPG-EYE board]] istructions.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Building_a_Mico32_platform_for_FPG-EYETutorial: Building a Mico32 platform for FPG-EYE2012-01-12T14:13:15Z<p>Erikadds: </p>
<hr />
<div>= Introduction =<br />
This page explains how to build a configuration file for FPG-EYE's fpga from a source platform with binary camera. <br />
Prerequisites:<br />
* [[Installation of Mico32/FPG-EYE development environment | Install Mico32/FPG-EYE development environment]] <br />
* Get a local copy of Erika repository to have the platform projects.<br />
For further info see this page:[[ERIKA_Enterprise_and_RT-Druid_SVN_Access#Anonymous.2C_readonly_access | ERIKA Enterprise and RT-Druid SVN Access instructions]].<br />
* To download the platform JEDEC file, you need a '''programming cable''' connected to the JTAG port of the board, follow the instructions on [[http://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_board | How programming the FPG-EYE board]].<br />
<br />
= Import platform project in LatticeMico System IDE =<br />
<br />
Launch [http://www.latticesemi.com/products/designsoftware/micodevelopmenttools/index.cfm ''LatticeMico System''] software, and click on '''MSB Perspective''' button (as the following figure):<br />
<br />
[[File:select_msb_from_msb_ide.png|center|thumb|700px| '''MSB''' button]]<br />
<br />
Open the '''Open Platform form''' by selecting the '''File->Open Platform''' menu item:<br />
<br />
[[File:open_msb_from_msb_ide.png|center|thumb|700px| Open '''MSB''' platform]]<br />
<br />
Click the '''Browse''' button and load '''ee/trunk/ee/examples/mico32/demo/platforms/fpg_eye_mico32/msb/soc/fpg_eye_mico32.msb''' file inside Erika repository local copy:<br />
<br />
[[File:Select_fpg_eye_mico32_msb_from_msb_ide.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'']]<br />
<br />
The platform's architecture is visible under '''Sources in Project''' window:<br />
<br />
[[File:fpg_eya_mico32_from_msb.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'' platform architecture]]<br />
<br />
Note: You don't need to make any changes to the platform.<br />
And finally, generate the platform source by selecting the '''Run Generator''' menu item:<br />
<br />
[[File:fpg_eya_mico32_from_msb_run.png|center|thumb|700px| Clicking on '''Run Generator''' we have the platform source]]<br />
<br />
The [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm mico32] platform's Verilog source is generated. To use this platform in FPG-EYE, the source code must be compiled in binary format.<br />
The next session explains how to compile the [http://www.verilog.com/ Verilog] platform's code with ispLEVER tool.<br />
<br />
= Import hardware platform project in ispLever IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLEVER] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_ispLever_ide.png|center|thumb|700px| ''Open project'' from ispLever]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/isplever/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_ispLever.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active.png|center|thumb|700px| ''ispLever'' project structure]]<br />
<br />
Before compiling the ispLever project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the ispLever ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the ispLever the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:camera_component_ngo_in ispLever.png|center|thumb|700px| ''camera_component_mod.ngo'' in ispLever project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the ispLEVER ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:isp_lever_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in ispLever project directory]]<br />
<br />
== Build the platform with ispLEVER ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Force''' :<br />
<br />
[[File:isp_lever_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_isplever.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Import hardware platform project in Diamond IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/diamond Diamond] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_diamond_ide.png|center|thumb|700px| ''Open project'' from Diamond]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/diamond/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_diamond.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active_diamond.png|center|thumb|700px| ''Diamond'' project structure]]<br />
<br />
Before compiling the Diamond project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the Diamond ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the Diamond the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:camera_component_ngo_in_diamond.png|center|thumb|700px| ''camera_component_mod.ngo'' in Diamond project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the Diamond ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:diamond_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in Diamond project directory]]<br />
<br />
== Build the platform with Diamond ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Return All''' :<br />
<br />
[[File:diamond_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_diamond.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Programming the platform on FPG-EYE board =<br />
The last step is download the '''JEDEC''' file into ''FPG-EYE''. Please follow the [[Programming the FPG-EYE board]] istructions.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Building_a_Mico32_platform_for_FPG-EYETutorial: Building a Mico32 platform for FPG-EYE2012-01-12T14:12:51Z<p>Erikadds: /* Introduction */</p>
<hr />
<div>= Introduction =<br />
This page explains how to build a configuration file for FPG-EYE's fpga from a source platform with binary camera. <br />
Prerequisites:<br />
* [[Installation of Mico32/FPG-EYE development environment | Install Mico32/FPG-EYE development environment]] <br />
* Get a local copy of Erika repository to have the platform projects.<br />
For further info see this page:[[ERIKA_Enterprise_and_RT-Druid_SVN_Access#Anonymous.2C_readonly_access | ERIKA Enterprise and RT-Druid SVN Access instructions]].<br />
* To download the platform JEDEC file, you need a <programming cable> connected to the JTAG port of the board, follow the instructions on [[http://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_board | How programming the FPG-EYE board]].<br />
<br />
= Import platform project in LatticeMico System IDE =<br />
<br />
Launch [http://www.latticesemi.com/products/designsoftware/micodevelopmenttools/index.cfm ''LatticeMico System''] software, and click on '''MSB Perspective''' button (as the following figure):<br />
<br />
[[File:select_msb_from_msb_ide.png|center|thumb|700px| '''MSB''' button]]<br />
<br />
Open the '''Open Platform form''' by selecting the '''File->Open Platform''' menu item:<br />
<br />
[[File:open_msb_from_msb_ide.png|center|thumb|700px| Open '''MSB''' platform]]<br />
<br />
Click the '''Browse''' button and load '''ee/trunk/ee/examples/mico32/demo/platforms/fpg_eye_mico32/msb/soc/fpg_eye_mico32.msb''' file inside Erika repository local copy:<br />
<br />
[[File:Select_fpg_eye_mico32_msb_from_msb_ide.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'']]<br />
<br />
The platform's architecture is visible under '''Sources in Project''' window:<br />
<br />
[[File:fpg_eya_mico32_from_msb.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'' platform architecture]]<br />
<br />
Note: You don't need to make any changes to the platform.<br />
And finally, generate the platform source by selecting the '''Run Generator''' menu item:<br />
<br />
[[File:fpg_eya_mico32_from_msb_run.png|center|thumb|700px| Clicking on '''Run Generator''' we have the platform source]]<br />
<br />
The [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm mico32] platform's Verilog source is generated. To use this platform in FPG-EYE, the source code must be compiled in binary format.<br />
The next session explains how to compile the [http://www.verilog.com/ Verilog] platform's code with ispLEVER tool.<br />
<br />
= Import hardware platform project in ispLever IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLEVER] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_ispLever_ide.png|center|thumb|700px| ''Open project'' from ispLever]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/isplever/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_ispLever.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active.png|center|thumb|700px| ''ispLever'' project structure]]<br />
<br />
Before compiling the ispLever project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the ispLever ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the ispLever the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:camera_component_ngo_in ispLever.png|center|thumb|700px| ''camera_component_mod.ngo'' in ispLever project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the ispLEVER ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:isp_lever_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in ispLever project directory]]<br />
<br />
== Build the platform with ispLEVER ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Force''' :<br />
<br />
[[File:isp_lever_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_isplever.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Import hardware platform project in Diamond IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/diamond Diamond] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_diamond_ide.png|center|thumb|700px| ''Open project'' from Diamond]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/diamond/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_diamond.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active_diamond.png|center|thumb|700px| ''Diamond'' project structure]]<br />
<br />
Before compiling the Diamond project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the Diamond ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the Diamond the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:camera_component_ngo_in_diamond.png|center|thumb|700px| ''camera_component_mod.ngo'' in Diamond project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the Diamond ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:diamond_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in Diamond project directory]]<br />
<br />
== Build the platform with Diamond ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Return All''' :<br />
<br />
[[File:diamond_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_diamond.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Programming the platform on FPG-EYE board =<br />
The last step is download the '''JEDEC''' file into ''FPG-EYE''. Please follow the [[Programming the FPG-EYE board]] istructions.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_Building_a_Mico32_platform_for_FPG-EYETutorial: Building a Mico32 platform for FPG-EYE2012-01-12T14:12:06Z<p>Erikadds: /* Introduction */</p>
<hr />
<div>= Introduction =<br />
This page explains how to build a configuration file for FPG-EYE's fpga from a source platform with binary camera. <br />
Prerequisites:<br />
* [[Installation of Mico32/FPG-EYE development environment | Install Mico32/FPG-EYE development environment]] <br />
* Get a local copy of Erika repository to have the platform projects.<br />
For further info see this page:[[ERIKA_Enterprise_and_RT-Druid_SVN_Access#Anonymous.2C_readonly_access | ERIKA Enterprise and RT-Druid SVN Access instructions]].<br />
* To download the platform JEDEC file, you need a programming cable connected to the JTAG port of the board, follow the instructions on [http://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_board | How programming the FPG-EYE board].<br />
<br />
= Import platform project in LatticeMico System IDE =<br />
<br />
Launch [http://www.latticesemi.com/products/designsoftware/micodevelopmenttools/index.cfm ''LatticeMico System''] software, and click on '''MSB Perspective''' button (as the following figure):<br />
<br />
[[File:select_msb_from_msb_ide.png|center|thumb|700px| '''MSB''' button]]<br />
<br />
Open the '''Open Platform form''' by selecting the '''File->Open Platform''' menu item:<br />
<br />
[[File:open_msb_from_msb_ide.png|center|thumb|700px| Open '''MSB''' platform]]<br />
<br />
Click the '''Browse''' button and load '''ee/trunk/ee/examples/mico32/demo/platforms/fpg_eye_mico32/msb/soc/fpg_eye_mico32.msb''' file inside Erika repository local copy:<br />
<br />
[[File:Select_fpg_eye_mico32_msb_from_msb_ide.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'']]<br />
<br />
The platform's architecture is visible under '''Sources in Project''' window:<br />
<br />
[[File:fpg_eya_mico32_from_msb.png|center|thumb|700px| Select ''fpg_eye_mico32.msb'' platform architecture]]<br />
<br />
Note: You don't need to make any changes to the platform.<br />
And finally, generate the platform source by selecting the '''Run Generator''' menu item:<br />
<br />
[[File:fpg_eya_mico32_from_msb_run.png|center|thumb|700px| Clicking on '''Run Generator''' we have the platform source]]<br />
<br />
The [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm mico32] platform's Verilog source is generated. To use this platform in FPG-EYE, the source code must be compiled in binary format.<br />
The next session explains how to compile the [http://www.verilog.com/ Verilog] platform's code with ispLEVER tool.<br />
<br />
= Import hardware platform project in ispLever IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLEVER] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_ispLever_ide.png|center|thumb|700px| ''Open project'' from ispLever]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/isplever/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_ispLever.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active.png|center|thumb|700px| ''ispLever'' project structure]]<br />
<br />
Before compiling the ispLever project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the ispLever ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the ispLever the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:camera_component_ngo_in ispLever.png|center|thumb|700px| ''camera_component_mod.ngo'' in ispLever project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the ispLEVER ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the ispLever project directory.<br />
<br />
[[File:isp_lever_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in ispLever project directory]]<br />
<br />
== Build the platform with ispLEVER ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Force''' :<br />
<br />
[[File:isp_lever_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_isplever.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Import hardware platform project in Diamond IDE =<br />
<br />
Open [http://www.latticesemi.com/products/designsoftware/diamond Diamond] and select ''Open Project'' under ''File menu'':<br />
<br />
[[File:open_project_from_diamond_ide.png|center|thumb|700px| ''Open project'' from Diamond]]<br />
<br />
Load '''ee/examples/mico32/demo/platforms/fpg_eye_mico32/diamond/fpg_eye_mico32.syn''' inside Erika repository local copy:<br />
<br />
[[File:fpg_eya_mico32_from_diamond.png|center|thumb|700px| Load ''fpg_eye_mico32.msb'']]<br />
<br />
The hardware project structure is visible under ''Sources in Project'' window. Ensure that ''fpg_eye_mico32_wrapper.v'' is selected and active:<br />
<br />
[[File:fpg_eye_mico32_wrapper_active_diamond.png|center|thumb|700px| ''Diamond'' project structure]]<br />
<br />
Before compiling the Diamond project, there are two more steps to perform (refer sections below).<br />
<br />
== Importing ''camera_component_mod.ngo'' in the Diamond ==<br />
<br />
The component camera installed in the platform ''fpg_eye_mico32'' is a binary version. So it is necessary to import in the Diamond the netlist of the camera. To do this, copy the file ''camera_component_mod.ngo'', from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:camera_component_ngo_in_diamond.png|center|thumb|700px| ''camera_component_mod.ngo'' in Diamond project directory]]<br />
<br />
== Importing ''meminit_ebr.mem'' bootloader file in the Diamond ==<br />
<br />
The file ''meminit_ebr.mem'' is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section [[Tutorial: Running ERIKA on Mico32 and FPG-EYE]]. Copy this file from the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet] to the Diamond project directory.<br />
<br />
[[File:diamond_mem_file.png|center|thumb|700px| ''meminit_ebr.mem'' in Diamond project directory]]<br />
<br />
== Build the platform with Diamond ==<br />
<br />
On '''Processes of current source''' click and select '''Generate Data File (JEDEC)''' then right click and select '''Return All''' :<br />
<br />
[[File:diamond_compile_fpg_eye_mico32.png|center|thumb|700px| '''Force''' from '''Generate Data File (JEDEC)''' menu]]<br />
<br />
When the process is complete the file the FPGA configuration file '''JEDEC''' is ready to use.<br />
<br />
[[File:generate_data_file_jedec_from_diamond.png|center|thumb|700px| '''Generate Data File (JEDEC)''']]<br />
<br />
= Programming the platform on FPG-EYE board =<br />
The last step is download the '''JEDEC''' file into ''FPG-EYE''. Please follow the [[Programming the FPG-EYE board]] istructions.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_boardProgramming the FPG-EYE board2012-01-12T14:00:15Z<p>Erikadds: /* Diamond Programmer */</p>
<hr />
<div>'''JEDEC''' is a ASCII text files containing programming information that can be used to configure a FPGA device. '''JEDEC''' is generated from [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] or [http://www.latticesemi.com/products/designsoftware/diamond Diamond] when a logic circuit is synthesized. <br />
It can be downloaded in the [http://www.latticesemi.com/ Lattice] device through the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] port . To do this two things are necessary:<br />
<br />
* Programming Cable.<br />
* Software: ispVM System or Diamond Programmer.<br />
<br />
== Programming Cable ==<br />
<br />
After completion of the logic design and creation of a programming file with the [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] software, is necessary a ''programming cable'' for programming the devices directly on the PC board. There are a lot of compatible Lattice ''programming cable''. This is very simple and low cost [http://www.latticesemi.com/products/developmenthardware/programmingcables.cfm programming cable].<br />
<br />
== ispVM System ==<br />
<br />
The [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ''ispVM''] software is default installed together [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] or [http://www.latticesemi.com/products/designsoftware/diamond Diamond] software. The default directory is <tt>(installation directory Lattice)/Accessories/ispVM System</tt><br />
<br />
* The ''programming cable'' must be connected to the FPG-EYE [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] board connector and PC port (can be Usb, serial or parallel).<br />
<br />
[[File:jtag_con.jpg|center|thumb|200px|Jtag connector]]<br />
<br />
* Turn on the power of the FPG-EYE board, and launch [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ispVM] software.<br />
<br />
[[File:open_ispVM.png|center|thumb|700px|Open ispVM software]]<br />
<br />
* Push '''Scan''' button, the software should find the Fpga model. If it don't be sure then the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] cable is connected and/or the FPG-EYE is powered.<br />
<br />
[[File:scan_ispVM.png|center|thumb|700px|Scan on ispVM software]]<br />
<br />
* Aftre click on '''FileName/IR-Lenght''' field will show the ''Chair Configuration'' window. With '''Browes''' button select '''jed''' file in local repository. <br />
<br />
[[File:select_file_ispVM.png|center|thumb|700px|Select jed file]]<br />
<br />
* Click on '''OK''' button and return on The [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ''ispVM''] main page. Click on '''GO''' and start the programming configuration in the FPGA. At end the board is ready for use.<br />
<br />
== Diamond Programmer ==<br />
<br />
* The ''programming cable'' must be connected to the FPG-EYE JTAG board connector and PC port (can be Usb, serial or parallel).<br />
* Turn on the power of the FPG-EYE board, and launch Diamond Programmer software.<br />
* Push '''Detect Cable''' button, the software should find the cable. <br />
* Select the Lattice Mico32 device and the JEDEC file as shown in the next figure.<br />
* From the menu, select 'Design -> Program' to load the platform on the device. At end the board is ready for use.<br />
<br />
[[File:Diamond_programmer.png|center|thumb|700px|Diamond Programmer]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=File:Diamond_programmer.pngFile:Diamond programmer.png2012-01-12T13:58:17Z<p>Erikadds: </p>
<hr />
<div></div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_boardProgramming the FPG-EYE board2012-01-12T13:57:44Z<p>Erikadds: </p>
<hr />
<div>'''JEDEC''' is a ASCII text files containing programming information that can be used to configure a FPGA device. '''JEDEC''' is generated from [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] or [http://www.latticesemi.com/products/designsoftware/diamond Diamond] when a logic circuit is synthesized. <br />
It can be downloaded in the [http://www.latticesemi.com/ Lattice] device through the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] port . To do this two things are necessary:<br />
<br />
* Programming Cable.<br />
* Software: ispVM System or Diamond Programmer.<br />
<br />
== Programming Cable ==<br />
<br />
After completion of the logic design and creation of a programming file with the [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] software, is necessary a ''programming cable'' for programming the devices directly on the PC board. There are a lot of compatible Lattice ''programming cable''. This is very simple and low cost [http://www.latticesemi.com/products/developmenthardware/programmingcables.cfm programming cable].<br />
<br />
== ispVM System ==<br />
<br />
The [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ''ispVM''] software is default installed together [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] or [http://www.latticesemi.com/products/designsoftware/diamond Diamond] software. The default directory is <tt>(installation directory Lattice)/Accessories/ispVM System</tt><br />
<br />
* The ''programming cable'' must be connected to the FPG-EYE [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] board connector and PC port (can be Usb, serial or parallel).<br />
<br />
[[File:jtag_con.jpg|center|thumb|200px|Jtag connector]]<br />
<br />
* Turn on the power of the FPG-EYE board, and launch [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ispVM] software.<br />
<br />
[[File:open_ispVM.png|center|thumb|700px|Open ispVM software]]<br />
<br />
* Push '''Scan''' button, the software should find the Fpga model. If it don't be sure then the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] cable is connected and/or the FPG-EYE is powered.<br />
<br />
[[File:scan_ispVM.png|center|thumb|700px|Scan on ispVM software]]<br />
<br />
* Aftre click on '''FileName/IR-Lenght''' field will show the ''Chair Configuration'' window. With '''Browes''' button select '''jed''' file in local repository. <br />
<br />
[[File:select_file_ispVM.png|center|thumb|700px|Select jed file]]<br />
<br />
* Click on '''OK''' button and return on The [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ''ispVM''] main page. Click on '''GO''' and start the programming configuration in the FPGA. At end the board is ready for use.<br />
<br />
== Diamond Programmer ==<br />
<br />
* The ''programming cable'' must be connected to the FPG-EYE JTAG board connector and PC port (can be Usb, serial or parallel).<br />
* Turn on the power of the FPG-EYE board, and launch Diamond Programmer software.<br />
* Push '''Detect Cable''' button, the software should find the cable. <br />
* Select the Lattice Mico32 device and the JEDEC file as shown in the next figure.<br />
* With 'Design -> Program' to load the platform on the device. At end the board is ready for use.<br />
<br />
[[File:Diamond_programmer.png|center|thumb|700px|Diamond Programmer]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Programming_the_FPG-EYE_boardProgramming the FPG-EYE board2012-01-12T13:45:50Z<p>Erikadds: </p>
<hr />
<div>'''JEDEC''' is a ASCII text files containing programming information that can be used to configure a FPGA device. '''JEDEC''' is generated from [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] or [http://www.latticesemi.com/products/designsoftware/diamond Diamond] when a logic circuit is synthesized. <br />
It can be downloaded in the [http://www.latticesemi.com/ Lattice] device through the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] port . To do this two things are necessary:<br />
<br />
* Programming Cable.<br />
* Software: ispVM System or Diamond Programmer.<br />
<br />
== Programming Cable ==<br />
<br />
After completion of the logic design and creation of a programming file with the [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] software, is necessary a ''programming cable'' for programming the devices directly on the PC board. There are a lot of compatible Lattice ''programming cable''. This is very simple and low cost [http://www.latticesemi.com/products/developmenthardware/programmingcables.cfm programming cable].<br />
<br />
== ispVM System ==<br />
<br />
The [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ''ispVM''] software is default installed together [http://www.latticesemi.com/products/designsoftware/isplever/isplever/index.cfm?source=sidebar ispLever] or [http://www.latticesemi.com/products/designsoftware/diamond Diamond] software. The default directory is <tt>(installation directory Lattice)/Accessories/ispVM System</tt><br />
<br />
* The ''programming cable'' must be connected to the FPG-EYE [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] board connector and PC port (can be Usb, serial or parallel).<br />
<br />
[[File:jtag_con.jpg|center|thumb|200px|Jtag connector]]<br />
<br />
* Turn on the power of the FPG-EYE board, and launch [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ispVM] software.<br />
<br />
[[File:open_ispVM.png|center|thumb|700px|Open ispVM software]]<br />
<br />
* Push '''Scan''' button, the software should find the Fpga model. If it don't be sure then the [http://en.wikipedia.org/wiki/Joint_Test_Action_Group JTAG] cable is connected and/or the FPG-EYE is powered.<br />
<br />
[[File:scan_ispVM.png|center|thumb|700px|Scan on ispVM software]]<br />
<br />
* Aftre click on '''FileName/IR-Lenght''' field will show the ''Chair Configuration'' window. With '''Browes''' button select '''jed''' file in local repository. <br />
<br />
[[File:select_file_ispVM.png|center|thumb|700px|Select jed file]]<br />
<br />
* Click on '''OK''' button and return on The [http://www.latticesemi.com/products/designsoftware/ispvmsystem/index.cfm ''ispVM''] main page. Click on '''GO''' and start the programming configuration in the FPGA. At end the board is ready for use.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Installation_of_Mico32/FPG-EYE_development_environmentInstallation of Mico32/FPG-EYE development environment2012-01-12T11:41:57Z<p>Erikadds: /* Introduction */</p>
<hr />
<div>= Introduction =<br />
<br />
This page describes a set of steps needed to compile and deploy a platform on FPG-EYE board.<br />
<br />
To begin with, following [http://www.latticesemi.com/licensing/index.cfm free license softwares from Lattice] must be installed in your environment:<br />
<br />
*[http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-07-55-23-01&source=sidebar ispLEVER] or [http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-07-55-23-01&source=sidebar Diamond]<br />
*[http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-07-30&source=sidebar ispVM System] or the Diamond programmer<br />
*[http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-07-20&source=sidebar LatticeMico System Development Tools (aka MSB)]<br />
<br />
Note:<br />
* Each version of ispLEVER or Diamond requires corresponding version of LatticeMico System Development Tools.<br />
* 64 bit OSes are not supported by ispLEVER (even though we were able to install it on a 64 bit Windows Vista/7, it is cumbersome).<br />
* The ispVM System must be version 18.0 or superior if you use ispLever.<br />
<br />
The entire FPG-EYE software has been developed with ispLEVER 8.0 and correspondant LatticeMico System Development Tools. It is assumed that all the tools are installed in the same base directory '''%ispTOOLS%'''. The support for Lattice Diamond is also available.<br />
<br />
In addition to lattice software you also need:<br />
* [http://erika.tuxfamily.org/erika-for-multiple-devices.html Evidence RT-Druid software] to run ERIKA Enterprise OS on Mico32 softcore<br />
* [http://www.python.org/ Python] installation with [http://pyserial.sourceforge.net/ pySerial module] to deploy your application on the FPG-EYE external flash, with Evidence's bootloader Mico32 application.<br />
<br />
= Standard Mico32 components Patches =<br />
<br />
During FPG-EYE software development a few bugs encountered in standard Mico32 components were corrected. Namely small bugs in following components:<br />
<br />
* SPI Flash Controller (Component directory: spi_flash. Verilog files: spi_flash_intf.v wb_intf.v) with version previous to v.1.1<br />
* Async SRAM Controller (Componet directory: asram_top. Verilog files: asram_core.v) with version previous to v.1.1<br />
<br />
The above mentioned bugs were of ispLEVER version 8.0 components. We are not sure if the same have been fixed in later versions.<br />
<br />
Patched verilog files can be found in [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet]. To apply these patches, you need to copy these new files in their respective components folders.<br />
<br />
The base directory for all the components is: <br />
<br />
<pre><br />
%ispTOOLS%\micosystem\components<br />
</pre><br />
<br />
Patched verilog files for each component must be placed in:<br />
<br />
<pre><br />
%ispTOOLS%\micosystem\components\<Component directory>\rtl\verilog<br />
</pre><br />
<br />
to fix the known bugs.<br />
<br />
= Evidence custom Mico32 components =<br />
<br />
FPG-EYE demo application uses a couple of custom Mico32 components: <br />
<br />
* Mico32_camera component (used to acquire frames from the cmos camera)<br />
* serial_io (used to access programmable DIP switches, LEDs, and peripherals power-off MOSFET switches) <br />
<br />
These components are available in [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE Software Packet], Mico32_camera as component binary, and serial_io directly as source code.<br />
<br />
To use these components in your platform, they must be imported inside the LatticeMico System Development Tools.<br />
<br />
== Import custom Mico32 components in LatticeMico System Development Tools ==<br />
<br />
Open your LatticeMico System Development Tool and on Available Components view click Import/Create custom Component button <br />
[[File:LatticeMicoSystem_import_button.png|center|thumb|200px| Available Components view Import/Create button.]]<br />
<br />
Select radio button Open component XML and load the xml component description file from the FPG-EYE software packet directory (e.g. '''FPG-EYE_software_packet\wishbone_components\mico32_camera\mico32_camera.xml''')<br />
[[File:LatticeMicoSystem_import_evidence_camera_component.png|center|thumb|200px| Import evidence camera component]]<br />
<br />
In our version of LatticeMico System Development Tools, sometimes for unknown reason, this procedure needs to be repeated more than once.<br />
[[File:LatticeMicoSystem_import_result.png|center|thumb|200px| Import Evidence custom components result]]<br />
<br />
= ERIKA and RT-Druid =<br />
<br />
[[Tutorial: Running ERIKA on Mico32 and FPG-EYE | FPG-EYE demo application]] is an ERIKA application, and to compile this, <br />
[[Tutorial: Installing ERIKA and RT-Druid, and compile your first application | ERIKA and RT-Druid]] softwares are required.<br />
<br />
= Python and pySerial module =<br />
<br />
To deploy a Mico32 application on the FPG-EYE external flash, Evidence provides a dedicated bootloader for FPG-EYE XP2. To interact with this bootloader, a python script is available with [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG_EYE Software Packet]. This python script has been written and tested on a python 2.x environment.<br />
<br />
== Installing Python on Windows ==<br />
<br />
Python can be installed on a windows machine in two different ways:<br />
* as native.<br />
* under cygwin.<br />
<br />
To install the native one just download the correct [http://www.python.org/download/ installer] and run it. If you want the cygwin version, just run the cygwin setup application and select python package.<br />
<br />
== Install pySerial on Windows ==<br />
<br />
If you have installed the native version of python, download the [http://pypi.python.org/pypi/pyserial pySerial installer] and run it.<br />
The easy way to install the pySerial module on cygwin is to install [http://pypi.python.org/pypi/setuptools python setuptools] first by running [http://peak.telecommunity.com/dist/ez_setup.py this script] in a Cygwin shell, and then, after the installation of the setuptools, just type:<br />
<pre><br />
easy_install pyserial<br />
</pre><br />
The setuptools will automatically select the right version of the module for your environment.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=FPG-EYE_hardware_and_softwareFPG-EYE hardware and software2012-01-12T11:37:38Z<p>Erikadds: /* FPG-EYE Software */</p>
<hr />
<div>The FPG-EYE is a development board produced by [http://www.evidence.eu.com/ Evidence S.r.l.].<br />
The board is based on Lattice core [http://www.latticesemi.com/products/fpga/xp2/index.cfm Lattice XP2-17 fpga]. This board can either be used as a standard fpga development board or as a [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm mico32] soft-core platform.<br />
<br />
== FPG-EYE Hardware ==<br />
<br />
The FPG-EYE is equipped with following onboard devices:<br />
* Fpga LFXP2-17<br />
* 25Mhz crystal oscillator<br />
* SRAM: 512 kB <br />
* SDRAM: 32 MB <br />
* Serial Flash: 4 MB<br />
* Leds and switches<br />
<br />
and additional external standard modules:<br />
* RS232 Transceiver<br />
* Ethernet module <br />
<br />
Following external modules are also available optionally: <br />
* CMOS Camera (Color) <br />
* RF Transceiver Module<br />
<br />
<br />
For more details, refer [http://www.evidence.eu.com/content/view/377/436/ Evidence FPG-EYE page]. In the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE software packet] you can find a [[Test hardware]] file. This [[Test hardware]] file tests all component device present on the FPG-EYE.<br />
<br />
== FPG-EYE Software ==<br />
<br />
The FPG-EYE board comes with a pre-loaded demo application, the Web-server Camera demo, which is hosted by a [http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm Mico32 platform]. <br />
The [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/mico32/demo/sw_projects/webserver_camera/ demo source files] can be found in the Erika examples.<br />
The Web-server Camera demo is an Erika-based application and uses Evidence custom components and platforms.<br />
The FPG-EYE custom components and the bootloader are contained in the [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE software packet] and can be freely downloaded. <br />
<br />
The [http://download.tuxfamily.org/erika/webdownload/fpg-eye/FPG-EYE_software_packet.zip FPG-EYE software packet] includes:<br />
* Evidence custom '''mico32_camera''' component (MSB component with binary netlist).<br />
* Evidence custom '''serpar_io''' component (MSB source component).<br />
* Binary external flash bootloader.<br />
* Python bootloader interface script.<br />
* Mico32 standard Async SRAM Controller and SPI Flash Controller components patched (only for Lattice ispLever, not required for Lattice Diamond).<br />
<br />
== Brief description of software components ==<br />
<br />
=== Evidence custom camera component ===<br />
<br />
The '''mico32_camera''' is a [http://www.google.it/url?sa=t&rct=j&q=wishobone%20bus&source=web&cd=2&ved=0CDAQFjAB&url=http%3A%2F%2Fsen.enst.fr%2Ffilemanager%2Factive%3Ffid%3D662&ei=w9GFTpHzLOqs0QW8wdH7Dw&usg=AFQjCNExXH_Cr7tBXmN2Gc9Kj9BDxAw8Bw&cad=rj wishbone] component developed by [http://www.evidence.eu.com/ Evidence S.r.l.]. It must be [[Installation_of_Mico32/FPG-EYE_development_environment#Import_custom_Mico32_components_in_LatticeMico_System_Development_Tools | imported in MSB's]] ''Available Components'', before using in platform designs.<br />
'''Mico32_camera''' comes with an [http://www.evidence.eu.com/content/view/27/254/ Erika] driver which is needed for developing your applications. <br />
<br />
Example of ''mico32_camera'' can be found under the section [[Camera API]]. <br />
To write your customised driver, refer [[Mico32_camera: Writing drivers based on mico32_camera]] page.<br />
<br />
=== Evidence custom serpar_io component ===<br />
<br />
This is a component developed by [http://www.evidence.eu.com/ Evidence S.r.l.]. Like any custom component, it must be [[Installation_of_Mico32/FPG-EYE_development_environment#Import_custom_Mico32_components_in_LatticeMico_System_Development_Tools | imported in MSB's]] before hand.<br />
<br />
It is basically a parallel to serial converter. The processor writes a datum on serpar_io component out register, that serializes it out to a [http://www.nxp.com/documents/data_sheet/74HC_HCT595.pdf 74hc595] (serial to parallel shift register) device. <br />
Similarly, serpar_io can get a serialized datum from [http://www.nxp.com/documents/data_sheet/74HC_HCT165.pdf 74hc165] (parallel to serial shift register) and puts it on the register so that the cpu can read it. The serial to parallel shift register enables/disables board peripherals power supply and LEDs, while the parallel to serial shift register reads switches the states.<br />
<br />
The [[sample code for serialpar_io]] shows a simple use of this component.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Tutorial:_RT-Druid_and_OIL_basicsTutorial: RT-Druid and OIL basics2012-01-12T11:21:20Z<p>Erikadds: /* Examples */</p>
<hr />
<div>OIL (OSEK Implementation Language) is a part of the OSEK/VDX standard, that isused for OS and application configuration. <br />
The specification of the OIL file structure and syntax is provided in the OSEK/VDX web site at http://www.osek-vdx.org. <br />
In the RT-Druid and in the Erika Enterprise RTOS the configuration of the system is defined inside an OIL file. <br />
In this web page we only provide a quick introduction of the OIL Language (for a complete description see the documentation <br />
at http://erika.tuxfamily.org/documentation.html), together with a specification of the specific OIL attributes implemented by RT-Druid.<br />
In Erika Enterprise all the RTOS objects like tasks, alarms, resources, are static and predefined at application compile time. <br />
To specify which objects exists in a particular application, Erika Enterprise uses the OIL Language, which is a simple text description language.<br />
Here is an example of the OIL File for the dsPIC (R) DSC device:<br><br />
<br />
CPU mySystem {<br><br />
:OS myOs {<br><br />
::EE_OPT = " DEBUG ";<br><br />
::CPU_DATA = PIC30 {<br><br />
:::APP_SRC = " code1.c";<br><br />
:::APP_SRC = " code2.c";<br><br />
:::MULTI_STACK = FALSE ;<br><br />
:::ICD2 = TRUE;<br><br />
::};<br><br />
::MCU_DATA = PIC30 {<br><br />
:::MODEL = 33 FFJ256GP710;<br><br />
::};<br><br />
::BOARD_DATA = EE_FLEX {<br><br />
:::USELEDS = TRUE;<br><br />
::}<br><br />
:};<br><br />
:TASK myTask {<br><br />
::PRIORITY = 1;<br><br />
::STACK = SHARED ;<br><br />
::SCHEDULE = FULL;<br><br />
:};<br><br />
:TASK myTask {<br><br />
::PRIORITY = 1;<br><br />
::STACK = SHARED ;<br><br />
::SCHEDULE = FULL;<br><br />
:};<br><br />
};<br><br />
<br />
The example contains a single object called CPU, which contains all the specifications and the values used by the system. <br />
Inside the CPU, are described the objects which are present in the application: <br />
an OS, which specifies the global attributes for the system, and, in the example, two TASKs.<br />
<br />
The OIL File is parsed by the RT-Druid code generator and, as a result, part of the RTOS source code is generated and compiled <br />
together with the application. An OIL file consists of two parts: a set of definitions and a set of declarations. <br />
Definitions are used to define data types, constants and kernel objects that need to be provided in the declaration part for <br />
configuring a specific kernel. In other words, the definition part tells the configurator that there exists different objects <br />
like tasks, resources, and so on, describing their attributes and types, like in a C struct declaration. Then, the declaration part <br />
is used to specify which objects are really present in a particular application.<br />
In RT-Druid, the definition part of the OIL file is fixed and is contained inside the RT-Druid Eclipse Plugins. <br />
The user has only to provide the declaration part, specifying for a particular application the objects to be created.<br />
<br />
The OIL file basically contains the description of a set of objects. A CPU is a container of these objects. <br />
Other objects include the following:<br />
* OS is the Operating System which runs on the CPU. This object contains all the global settings which influence the compilation <br />
process and the customization of the Erika Enterprise RTOS.<br />
* APPMODE defines the different application mode. These modes are then used to control the autostart feature for tasks and alarms in the OIL file.<br />
* TASK is an application task handled by the OS.<br />
* RESOURCE is a resource (basically a binary mutex) used for mutual exclusion.<br />
* EVENT is a synchronization flag used by extended tasks.<br />
* COUNTER is a software source for periodic / one shot alarms.<br />
* ALARM is a notification mechanism attached to a counter which can be used to activate a task, set an event, or call a function.<br />
All the attributes in the OIL file can be:<br />
* numbers, i.e. the PRIORITY attribute;<br />
* strings, i.e. the APP_SRC attribute;<br />
* enumerations, i.e. the KERNEL_TYPE attribute.<br />
<br />
The OIL file includes a set of fields for controlling the command line parameters which are passed to the compiler tools. <br />
The meaning of those elements is the following:<br />
* EE_OPT contains a list of additional compilation flags passed to the Erika Enterprise makefile. <br />
In practice, the EE_OPT makefile variable controls which files has to be compiled and with which options. <br />
The EE_OPT attributes are translated in #defines in the C code.<br />
* CFLAGS contains the list of additional C compiler options.<br />
* ASFLAGS contains the list of additional assembly options.<br />
* LDFLAGS Contains the list of additional linker parameters.<br />
* LDDEPS Contains the list of additional library dependencies which have to be added to the makefile rules.<br />
* LIBS Contains the list of additional libraries that needs to be linked.<br />
Example of declaration:<br />
<br />
CPU mySystem {<br><br />
:OS myOs {<br><br />
::EEOPT = " MYFLAG1 ";<br><br />
::EEOPT = " MYFLAG2 ";<br><br />
::CFLAGS = "-G0 ";<br><br />
::CFLAGS = "-O0 -g";<br><br />
::CFLAGS = "- Wall -Wl ,-Map -Wl , project .map ";<br><br />
::ASFLAGS = "-g";<br><br />
::LIBS = "-lm ";<br><br />
::...<br><br />
:};<br><br />
...<br><br />
}<br><br />
<br />
The CPU_DATA section of the OS object is used to specify the configuration of a core in a single or in a multiple core device.<br />
The MCU_DATA section of the OS object is used to specify the configuration of peripherals which are present in a specific microcontroller.<br />
The BOARD_DATA section of the OS object is used to specify the configuration of the board where the microcontroller is placed. <br />
For example, the board configuration includes the configuration of the external devices like leds, buttons, displays, and other peripherals.<br />
The OIL file can specify a set of libraries which are distributed with or are supported by Erika Enterprise and that have to be linked <br />
together with the application. The specification is done by using the LIB attribute.<br />
The list of supported libraries depends on the target and can be found in the Erika Enterprise Manual for the specific target. <br />
Libraries which are not directly supported by Erika Enterprise can be added directly by specifying the appropriate linker parameters in<br />
the LDFLAGS attribute of the OS object.<br />
<br />
== Examples ==<br />
* [[OIL file for Lattice Mico32]]<br />
* [http://erika.tuxfamily.org/wiki/index.php?title=OIL_example_for_Freescale_S12 OIL file for Freescale S12]<br />
<br />
== See also ==<br />
* [[Tutorial: Installing ERIKA and RT-Druid, and compile your first application]]<br />
* [[EEOPT]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=OIL_example_for_Freescale_S12OIL example for Freescale S122012-01-12T11:20:11Z<p>Erikadds: Created page with "* OIL example for Freescale S12: CPU test_application { OS EE { EE_OPT = "__ASSERT__"; // to use assertion mechanism EE_OPT = "DEBUG"; // to include de..."</p>
<hr />
<div>* OIL example for Freescale S12:<br />
<br />
CPU test_application {<br />
OS EE {<br />
EE_OPT = "__ASSERT__"; // to use assertion mechanism<br />
EE_OPT = "DEBUG"; // to include debug info<br />
EE_OPT = "__CODEWARRIOR__"; // to use CODEWARRIOR compiler otherwise COSMIC compiler will be used.<br />
EE_OPT = "CW_EVAL_VERSION"; // If the Codewarrior compiler license is expired use this <br />
// option to avoid syntax errors during the compilation.<br />
CFLAGS = "-D__FAR_DATA"; // Options for the C compiler (refer to the compiler manual)<br />
ASFLAGS = ""; // Options for the assembler (refer to the assembler manual)<br />
LDFLAGS = "-addansibi.lib"; // Options for the linker (refer to the linker manual)<br />
CPU_DATA = MC9S12 { // CPU section<br />
APP_SRC = "code.c"; // Specify source files in this section...<br />
APP_SRC = "Vectors.c";<br />
APP_SRC = "CPU12ISRs.c";<br />
APP_SRC = "Start12.c";<br />
MULTI_STACK = FALSE;<br />
};<br />
MCU_DATA = MC9S12 { // MCU section<br />
MODEL = CUSTOM{ // Allowed values for S12 are: MC9S12G128, MC9S12XS128, CUSTOM<br />
// MC9S12G128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12G128.prm (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12g128.h (from the CW compiler installation directory)<br />
// Codewarrior SRC: mc9s12g128.c (from the CW compiler installation directory)<br />
// No Cosmic support for MC9S12G128 <br />
// MC9S12XS128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12XS128.prm (in ee\pkg\mcu\hs12xs)<br />
// Cosmic Linker script: MC9S12XS128.lkf (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12xs128.h (from the compiler installation directory)<br />
// Cosmic Header: ioxs256.h (from the compiler installation directory)<br />
// Codewarrior SRC: mc9s12xs128.c (from the compiler installation directory)<br />
// Cosmic SRC: nothing<br />
// CUSTOM model can be used to change default settings.<br />
MODEL = "MC9S12G128"; // Device model<br />
LINKERSCRIPT = "../mc9s12g128.prm"; // User linker script. If this field is void, a default linker script will be used.<br />
INCLUDE_H = "mc9s12g128.h"; // Header from user or compiler folder. <br />
INCLUDE_C = "mc9s12g128.c"; // Registers definition file from user or compiler folder.<br />
INCLUDE_S = ""; // ASM file for startup if needed.<br />
};<br />
TIMER = TRUE; // This options enables timer driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_TIMER__, __USE_PIT__<br />
// MC9S12G128: __USE_TIMER__ <br />
SERIAL = TRUE; // This options enables serial interface driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_SCI__<br />
// MC9S12G128: __USE_SCI__<br />
};<br />
STATUS = EXTENDED; // Kernel configuration <br />
STARTUPHOOK = FALSE;<br />
ERRORHOOK = FALSE;<br />
SHUTDOWNHOOK = FALSE;<br />
PRETASKHOOK = FALSE;<br />
POSTTASKHOOK = FALSE;<br />
USEGETSERVICEID = FALSE;<br />
USEPARAMETERACCESS = FALSE;<br />
USERESSCHEDULER = TRUE;<br />
KERNEL_TYPE = BCC1; // Kernel type <br />
};<br />
/* Here you can specify tasks, alarms, events, counters, ... */<br />
TASK Task1 {<br />
PRIORITY = 1;<br />
ACTIVATION = 1;<br />
SCHEDULE = FULL;<br />
AUTOSTART = TRUE;<br />
STACK = SHARED;<br />
};<br />
COUNTER Counter1 {<br />
MINCYCLE = 2;<br />
MAXALLOWEDVALUE = 16 ;<br />
TICKSPERBASE = 1;<br />
};<br />
ALARM Alarm1 {<br />
COUNTER = "Counter1";<br />
ACTION = ACTIVATETASK { TASK = "Task1"; };<br />
AUTOSTART = FALSE;<br />
};<br />
};</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Freescale_S12Freescale S122012-01-12T11:19:52Z<p>Erikadds: /* Examples */</p>
<hr />
<div>= Freescale S12 support =<br />
ERIKA Enterprise supports Freescale HCS12 microcontrollers. <br />
The support for RT-Druid is now available .<br><br />
The HCS12 support includes: <br />
# support for '''COSMIC''' compiler (only for HCS12XS, since Erika release 1.5.0) <br />
# support for '''CODEWARRIOR CWS12v5.1''' compiler (since Erika release 1.6.0).<br />
# support for single and multi stack configurations.<br />
# ISR interrupt supported.<br />
# support for Freescale HIWAVE Debugger.<br />
<br />
* '''Supported compiler'''<br />
** COSMIC C cross compiler and ELF module generation for debugging information.<br />
** CODEWARRIOR CWS12v5.1 compiler and ELF module generation for debugging information.<br />
::* CODEWARRIOR compiler is enabled adding this option in the conf.oil file:<br />
EE_OPT = "__CODEWARRIOR__";<br />
::* If the compiler evaluation license is expired, you may have to add also this option to avoid syntax errors during the compilation:<br />
EE_OPT = "CW_EVAL_VERSION"; <br />
* '''Mode of operation'''<br />
** ''Mono-stack'': The Monostack configuration of the ERIKA Kernel models the fact that all tasks and ISRs in the system share the same stack.<br />
** ''Multi-stack'': Every thread can have its private stack, or it can share it with other threads. <br />
<br />
* '''Handling of paging registers'''<br />
:The compiler supports bank switching for code and data, using the internal window mechanism provided by the HCS12 processor.<br />
:Bank switching mechanism delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.<br />
:Bank switching is supported via:<br />
:- @far type qualifier to describe a function relocated in a different bank. Calling such a function implies a special calling <br />
:sequence, and a special return sequence. Such a function has to be defined @far and referenced as @far in all the files using <br />
:it. The COSMIC compiler also provides a specific option +modf to automatically consider all the functions to be @far. The @far type <br />
:modifier is also used to declared variables allocated in a data bank.<br />
:- Linker options are required to ensure proper physical and logical addresses computations. The linker is also able to <br />
:automatically fill banks without any need to take care of the page boundaries.<br />
<br />
= CPUs =<br />
* '''S12 Hardware Abstraction Layer''' (since Erika revision 1531): S12 HAL now integrates the Erika HAL common files (see [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/cpu/common/ 'pkg/cpu/common'] folder and [http://erika.tuxfamily.org/wiki/index.php?title=Common_files_for_the_HAL Common_files_for_the_HAL] for further info). This feature simplifies future extensions for other S12 devices and ensures greater code stability against changes to the kernel code.<br />
* '''Nesting of interrupts''':<br />
** ''MC9s12XS128'': The IPL bits allow the nesting of interrupts, blocking interrupts of an equal or lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.<br />
** ''MC9S12G128'': <pre style="color:red">WARNING: MC9S12G128 doesn't support IPL mechanism.</pre> To enable the nesting of interrupts in the code, the user should clear I bit (in the CCR register) inside the interrupt service routine and after the peripheral interrupt flag has been cleared. If the I bit is cleared before the peripheral interrupt flag has been cleared the CPU restarts the interrupt creating an infinite loop. For this reason I-bit cannot be cleared inside Erika HAL files and this task is left to the user. To enable the compilation of the code for the nesting of interrupts the symbol<br />
__ALLOW_NESTED_IRQ__<br />
must be defined.<br />
Note: If the kernel type is FP the nesting of the interrupts can be enabled in this way:<br />
KERNEL_TYPE = FP{<br />
NESTED_IRQ = TRUE;<br />
}; <br />
otherwise the default case is FALSE and the nesting of the interrupts is disabled.<br />
<br />
= MCUs =<br />
<br />
* The MCUs currently supported are the following:<br />
** ''Freescale'' '''MC9S12XS128'''<br />
** ''Freescale'' '''MC9S12G128'''<br />
<br />
* List of functions:<br />
** ''Periodic interrupt timer''<br />
*** void EE_pit0_init( unsigned char pitmtld0, unsigned char pitld0, unsigned char prio ); // To init PIT0<br />
*** void EE_pit0_close( void ); // To close PIT0<br />
*** void EE_pit0_clear_ISRflag( void ); // To clean PIT0 ISR flag <br />
** ''Serial communication interface''<br />
*** void EE_sci_open(unsigned char sci_num, unsigned long int baudrate); // Open the serial interface. Requires: EE_set_peripheral_frequency_mhz(f_mhz) <br />
*** void EE_sci_close(unsigned char sci_num); // To close the serial interface<br />
*** Bool EE_sci_send_byte(unsigned char sci_num, unsigned char buffer); // To send a byte<br />
*** Bool EE_sci_send_string(unsigned char sci_num, const char* s, unsigned int num); // to send a string<br />
*** Bool EE_sci_send_bytes(unsigned char sci_num, char* v, unsigned int num); // To send a vector of bytes<br />
*** Bool EE_sci_get_byte(unsigned char sci_num, unsigned char *buffer); // to get a byte<br />
*** Bool EE_sci_getcheck(unsigned char sci_num); // to check the serial reception of a byte<br />
** ''Timer''<br />
*** int EE_timer_init_us(EE_UINT16 tim_id, EE_UINT32 period_us, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** int EE_timer_init_ms(EE_UINT16 tim_id, EE_UINT16 period_ms, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** void EE_timer_start() // start timer<br />
*** void EE_timer_stop() // stop timer<br />
*** void EE_timer_reset() // reset timer<br />
*** void EE_timer_clear_ISRflag(EE_UINT16 tim_id) // clear interrrupt flag<br />
*** EE_UINT16 EE_timer_get_counter() // get counter<br />
*** void EE_timer_enable_ISR(EE_UINT16 tim_id, EE_UINT8 isr_mode) // enable IRQ<br />
** void EE_timer_disable_ISR(EE_UINT16 tim_id) // disable IRQ<br />
<br />
= Boards =<br />
<br />
* The boards currently supported are the following:<br />
** ''SofTec Microsystems'' '''DEMO9S12XSFAME''' demo board.<br />
** ''Freescale Axiom'' '''TWRS12G128''' evaluation board.<br />
<br />
<br />
* '''DEMO9S12XSFAME''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/hs12xs_demo9s12xsfame/ demo9s12xsfame])<br />
** void EE_demo9s12xsfame_leds_init(void); // To configure the leds port <br />
** void EE_demo9s12xsfame_leds( EE_UINT8 data ); // To set the led port vaules <br />
** void EE_demo9s12xsfame_led_0_on(void); // To turn on LED0<br />
** void EE_demo9s12xsfame_led_0_off(void); // To turn off LED0<br />
** void EE_demo9s12xsfame_led_1_on(void); // To turn on LED1<br />
** void EE_demo9s12xsfame_led_1_off(void); // To turn off LED1<br />
** void EE_demo9s12xsfame_led_2_on(void); // To turn on LED2<br />
** void EE_demo9s12xsfame_led_2_off(void); // To turn off LED2<br />
** void EE_demo9s12xsfame_led_3_on(void); // To turn on LED3<br />
** void EE_demo9s12xsfame_led_3_off(void); // To turn off LED3<br />
** void EE_demo9s12xsfame_leds_on(void); // To turn on all the leds<br />
** void EE_demo9s12xsfame_leds_off(void); // To turn off all the leds<br />
** void EE_demo9s12xsfame_buttons_init( EE_UINT8 bx, EE_UINT8 prio ); // To init the buttons port<br />
** void EE_demo9s12xsfame_buttons_close( void ); // To reset the buttons port<br />
** void EE_demo9s12xsfame_buttons_disable_interrupts( EE_UINT8 bx ); // To disable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_enable_interrupts( EE_UINT8 bx ); // To enable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_clear_ISRflag( EE_UINT8 bx ); // To clear button ISR flag<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B0( void ); // To get the BUTTON0 value<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B1( void ); // To get the BUTTON1 value<br />
** void EE_demo9s12xsfame_adc_init( unsigned char res, unsigned char numconvseq ); // To init ADC<br />
** void EE_demo9s12xsfame_adc_convert( void ); // To start conversion<br />
** unsigned int EE_demo9s12xsfame_adc_getvalue( unsigned int adcch ); // To get a value<br />
** void EE_demo9s12xsfame_adc_close( void ); // To close ADC<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_light( void ); // To get light sensor value<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_pot( void ); // To get potentiometer value<br />
<br />
<br />
* '''TWRS12G128''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/twrs12g128/ twrs12g128])<br />
** void EE_leds_init() or EE_twrs12g128_leds_init()<br />
** void EE_leds(EE_UINT8 data) or EE_twrs12g128_leds(EE_UINT8 data)<br />
** void EE_led_1_on() or EE_twrs12g128_led_1_on() <br />
** void EE_led_1_off() or EE_twrs12g128_led_1_off() <br />
** void EE_led_2_on() or EE_twrs12g128_led_2_on() <br />
** void EE_led_2_off() or EE_twrs12g128_led_2_off() <br />
** void EE_led_3_on() or EE_twrs12g128_led_3_on() <br />
** void EE_led_3_off() or EE_twrs12g128_led_3_off() <br />
** void EE_led_4_on() or EE_twrs12g128_led_4_on() <br />
** void EE_led_4_off() or EE_twrs12g128_led_4_off()<br />
** void EE_led_1_toggle() or EE_twrs12g128_led_1_toggle()<br />
** void EE_led_2_toggle() or EE_twrs12g128_led_2_toggle()<br />
** void EE_led_3_toggle() or EE_twrs12g128_led_3_toggle()<br />
** void EE_led_4_toggle() or EE_twrs12g128_led_4_toggle()<br />
** void EE_leds_on() or EE_twrs12g128_leds_on() <br />
** void EE_leds_off() or EE_twrs12g128_leds_off() <br />
** void EE_buttons_init(EE_UINT8 bx) or EE_twrs12g128_buttons_init(EE_UINT8 bx)<br />
** void EE_buttons_close or EE_twrs12g128_buttons_close()<br />
** EE_UINT8 EE_button_get_B1() or EE_twrs12g128_button_get_B1()<br />
** EE_UINT8 EE_button_get_B2() or EE_twrs12g128_button_get_B2()<br />
** EE_UINT8 EE_button_get_B3() or EE_twrs12g128_button_get_B3()<br />
** EE_UINT8 EE_button_get_B4() or EE_twrs12g128_button_get_B4()<br />
<br />
= Examples =<br />
<br />
* The examples and tests are available in this folders:<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12xs/ S12XS examples]<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12g/ S12G examples]<br />
<br />
= Download and install =<br />
<br />
RT-Druid and Erika Enterprise RTOS (version 1.6.0), for Microsoft Windows, can be freely downloaded from the following web address:<br />
* [http://download.tuxfamily.org/erika/webdownload/eeb_gpl/EE_160_Win.zip EE_160_Win.zip]<br />
<br />
Once downloaded, extract all the files contained in it and copy the folder named ''eclipse'' in your preferred directory on your PC (a recommended path is: C:\Evidence\).<br />
Now, launch the program by double-clicking on the executable ''eclipse.exe''inside the ''C:\Evidence\eclipse'' folder and choose the path of your workspace.<br />
The workspace is the default working directory in which the projects will be created. <br />
<br />
<br />
If you want to download only a selected revision of the kernel, open the Cygwin shell and get an anonymous SVN checkout typing this command:<br />
svn co svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/ee/trunk/ee -r number_of_revision<br />
<br />
Note: <br />
Cygwin can be downloaded from this web site: http://www.cygwin.com/ <br />
To use SVN, the Cygwin SVN package must to be installed using the Cygwin Setup utility.<br />
<br />
<br />
To update your RT-DRUID version:<br />
* Open the “Help” menu item and selecting “Install New Software” (see image below).<br />
[[image:install_new_sw.PNG|center|100px]]<br />
* Then add, for example, the following path: [http://download.tuxfamily.org/erika/webdownload/rtdruid_160_nb/]<br />
* To add a new web address, clicking on “Add” and write the desired address in the filed “Location” (see image below).<br />
[[image:add_web_address.PNG|center|100px]]<br />
* Select all the plugins and click on the “Next” button. Then click again on “Next”, read the conditions and ''in case'' accept them by clicking on the “Finish” button.<br />
* Wait for the completion of the update and restart before using the software.<br />
<br />
<br />
'''Warnings and recommendations''' <br />
* For a fast installation deselect ''Contact all update sites during install to find required software''.<br />
* The revision '''1543''' of '''RT-Druid''' and '''Erika''' has been tested on the MODISTARC testcase, so this version is recommended.<br />
* However, the new Erika HCS12 package can work also with the previous versions of RT-Druid.<br />
<br />
= How to build a project in RT-DRUID =<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12XS]]<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12G]]<br />
* [[Tutorial: S12XS - First installation and application compilation on Windows]]<br />
* [[OIL example for Freescale S12]]<br />
<br />
= How to run MODISTARC regression tests =<br />
* [[A brief description on how to run MODISTARC regression tests for Freescale S12XS]]<br />
<br />
<br />
[[Category:Supported Devices]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Freescale_S12Freescale S122012-01-12T11:19:30Z<p>Erikadds: /* How to build a project in RT-DRUID */</p>
<hr />
<div>= Freescale S12 support =<br />
ERIKA Enterprise supports Freescale HCS12 microcontrollers. <br />
The support for RT-Druid is now available .<br><br />
The HCS12 support includes: <br />
# support for '''COSMIC''' compiler (only for HCS12XS, since Erika release 1.5.0) <br />
# support for '''CODEWARRIOR CWS12v5.1''' compiler (since Erika release 1.6.0).<br />
# support for single and multi stack configurations.<br />
# ISR interrupt supported.<br />
# support for Freescale HIWAVE Debugger.<br />
<br />
* '''Supported compiler'''<br />
** COSMIC C cross compiler and ELF module generation for debugging information.<br />
** CODEWARRIOR CWS12v5.1 compiler and ELF module generation for debugging information.<br />
::* CODEWARRIOR compiler is enabled adding this option in the conf.oil file:<br />
EE_OPT = "__CODEWARRIOR__";<br />
::* If the compiler evaluation license is expired, you may have to add also this option to avoid syntax errors during the compilation:<br />
EE_OPT = "CW_EVAL_VERSION"; <br />
* '''Mode of operation'''<br />
** ''Mono-stack'': The Monostack configuration of the ERIKA Kernel models the fact that all tasks and ISRs in the system share the same stack.<br />
** ''Multi-stack'': Every thread can have its private stack, or it can share it with other threads. <br />
<br />
* '''Handling of paging registers'''<br />
:The compiler supports bank switching for code and data, using the internal window mechanism provided by the HCS12 processor.<br />
:Bank switching mechanism delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.<br />
:Bank switching is supported via:<br />
:- @far type qualifier to describe a function relocated in a different bank. Calling such a function implies a special calling <br />
:sequence, and a special return sequence. Such a function has to be defined @far and referenced as @far in all the files using <br />
:it. The COSMIC compiler also provides a specific option +modf to automatically consider all the functions to be @far. The @far type <br />
:modifier is also used to declared variables allocated in a data bank.<br />
:- Linker options are required to ensure proper physical and logical addresses computations. The linker is also able to <br />
:automatically fill banks without any need to take care of the page boundaries.<br />
<br />
= CPUs =<br />
* '''S12 Hardware Abstraction Layer''' (since Erika revision 1531): S12 HAL now integrates the Erika HAL common files (see [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/cpu/common/ 'pkg/cpu/common'] folder and [http://erika.tuxfamily.org/wiki/index.php?title=Common_files_for_the_HAL Common_files_for_the_HAL] for further info). This feature simplifies future extensions for other S12 devices and ensures greater code stability against changes to the kernel code.<br />
* '''Nesting of interrupts''':<br />
** ''MC9s12XS128'': The IPL bits allow the nesting of interrupts, blocking interrupts of an equal or lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.<br />
** ''MC9S12G128'': <pre style="color:red">WARNING: MC9S12G128 doesn't support IPL mechanism.</pre> To enable the nesting of interrupts in the code, the user should clear I bit (in the CCR register) inside the interrupt service routine and after the peripheral interrupt flag has been cleared. If the I bit is cleared before the peripheral interrupt flag has been cleared the CPU restarts the interrupt creating an infinite loop. For this reason I-bit cannot be cleared inside Erika HAL files and this task is left to the user. To enable the compilation of the code for the nesting of interrupts the symbol<br />
__ALLOW_NESTED_IRQ__<br />
must be defined.<br />
Note: If the kernel type is FP the nesting of the interrupts can be enabled in this way:<br />
KERNEL_TYPE = FP{<br />
NESTED_IRQ = TRUE;<br />
}; <br />
otherwise the default case is FALSE and the nesting of the interrupts is disabled.<br />
<br />
= MCUs =<br />
<br />
* The MCUs currently supported are the following:<br />
** ''Freescale'' '''MC9S12XS128'''<br />
** ''Freescale'' '''MC9S12G128'''<br />
<br />
* List of functions:<br />
** ''Periodic interrupt timer''<br />
*** void EE_pit0_init( unsigned char pitmtld0, unsigned char pitld0, unsigned char prio ); // To init PIT0<br />
*** void EE_pit0_close( void ); // To close PIT0<br />
*** void EE_pit0_clear_ISRflag( void ); // To clean PIT0 ISR flag <br />
** ''Serial communication interface''<br />
*** void EE_sci_open(unsigned char sci_num, unsigned long int baudrate); // Open the serial interface. Requires: EE_set_peripheral_frequency_mhz(f_mhz) <br />
*** void EE_sci_close(unsigned char sci_num); // To close the serial interface<br />
*** Bool EE_sci_send_byte(unsigned char sci_num, unsigned char buffer); // To send a byte<br />
*** Bool EE_sci_send_string(unsigned char sci_num, const char* s, unsigned int num); // to send a string<br />
*** Bool EE_sci_send_bytes(unsigned char sci_num, char* v, unsigned int num); // To send a vector of bytes<br />
*** Bool EE_sci_get_byte(unsigned char sci_num, unsigned char *buffer); // to get a byte<br />
*** Bool EE_sci_getcheck(unsigned char sci_num); // to check the serial reception of a byte<br />
** ''Timer''<br />
*** int EE_timer_init_us(EE_UINT16 tim_id, EE_UINT32 period_us, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** int EE_timer_init_ms(EE_UINT16 tim_id, EE_UINT16 period_ms, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** void EE_timer_start() // start timer<br />
*** void EE_timer_stop() // stop timer<br />
*** void EE_timer_reset() // reset timer<br />
*** void EE_timer_clear_ISRflag(EE_UINT16 tim_id) // clear interrrupt flag<br />
*** EE_UINT16 EE_timer_get_counter() // get counter<br />
*** void EE_timer_enable_ISR(EE_UINT16 tim_id, EE_UINT8 isr_mode) // enable IRQ<br />
** void EE_timer_disable_ISR(EE_UINT16 tim_id) // disable IRQ<br />
<br />
= Boards =<br />
<br />
* The boards currently supported are the following:<br />
** ''SofTec Microsystems'' '''DEMO9S12XSFAME''' demo board.<br />
** ''Freescale Axiom'' '''TWRS12G128''' evaluation board.<br />
<br />
<br />
* '''DEMO9S12XSFAME''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/hs12xs_demo9s12xsfame/ demo9s12xsfame])<br />
** void EE_demo9s12xsfame_leds_init(void); // To configure the leds port <br />
** void EE_demo9s12xsfame_leds( EE_UINT8 data ); // To set the led port vaules <br />
** void EE_demo9s12xsfame_led_0_on(void); // To turn on LED0<br />
** void EE_demo9s12xsfame_led_0_off(void); // To turn off LED0<br />
** void EE_demo9s12xsfame_led_1_on(void); // To turn on LED1<br />
** void EE_demo9s12xsfame_led_1_off(void); // To turn off LED1<br />
** void EE_demo9s12xsfame_led_2_on(void); // To turn on LED2<br />
** void EE_demo9s12xsfame_led_2_off(void); // To turn off LED2<br />
** void EE_demo9s12xsfame_led_3_on(void); // To turn on LED3<br />
** void EE_demo9s12xsfame_led_3_off(void); // To turn off LED3<br />
** void EE_demo9s12xsfame_leds_on(void); // To turn on all the leds<br />
** void EE_demo9s12xsfame_leds_off(void); // To turn off all the leds<br />
** void EE_demo9s12xsfame_buttons_init( EE_UINT8 bx, EE_UINT8 prio ); // To init the buttons port<br />
** void EE_demo9s12xsfame_buttons_close( void ); // To reset the buttons port<br />
** void EE_demo9s12xsfame_buttons_disable_interrupts( EE_UINT8 bx ); // To disable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_enable_interrupts( EE_UINT8 bx ); // To enable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_clear_ISRflag( EE_UINT8 bx ); // To clear button ISR flag<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B0( void ); // To get the BUTTON0 value<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B1( void ); // To get the BUTTON1 value<br />
** void EE_demo9s12xsfame_adc_init( unsigned char res, unsigned char numconvseq ); // To init ADC<br />
** void EE_demo9s12xsfame_adc_convert( void ); // To start conversion<br />
** unsigned int EE_demo9s12xsfame_adc_getvalue( unsigned int adcch ); // To get a value<br />
** void EE_demo9s12xsfame_adc_close( void ); // To close ADC<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_light( void ); // To get light sensor value<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_pot( void ); // To get potentiometer value<br />
<br />
<br />
* '''TWRS12G128''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/twrs12g128/ twrs12g128])<br />
** void EE_leds_init() or EE_twrs12g128_leds_init()<br />
** void EE_leds(EE_UINT8 data) or EE_twrs12g128_leds(EE_UINT8 data)<br />
** void EE_led_1_on() or EE_twrs12g128_led_1_on() <br />
** void EE_led_1_off() or EE_twrs12g128_led_1_off() <br />
** void EE_led_2_on() or EE_twrs12g128_led_2_on() <br />
** void EE_led_2_off() or EE_twrs12g128_led_2_off() <br />
** void EE_led_3_on() or EE_twrs12g128_led_3_on() <br />
** void EE_led_3_off() or EE_twrs12g128_led_3_off() <br />
** void EE_led_4_on() or EE_twrs12g128_led_4_on() <br />
** void EE_led_4_off() or EE_twrs12g128_led_4_off()<br />
** void EE_led_1_toggle() or EE_twrs12g128_led_1_toggle()<br />
** void EE_led_2_toggle() or EE_twrs12g128_led_2_toggle()<br />
** void EE_led_3_toggle() or EE_twrs12g128_led_3_toggle()<br />
** void EE_led_4_toggle() or EE_twrs12g128_led_4_toggle()<br />
** void EE_leds_on() or EE_twrs12g128_leds_on() <br />
** void EE_leds_off() or EE_twrs12g128_leds_off() <br />
** void EE_buttons_init(EE_UINT8 bx) or EE_twrs12g128_buttons_init(EE_UINT8 bx)<br />
** void EE_buttons_close or EE_twrs12g128_buttons_close()<br />
** EE_UINT8 EE_button_get_B1() or EE_twrs12g128_button_get_B1()<br />
** EE_UINT8 EE_button_get_B2() or EE_twrs12g128_button_get_B2()<br />
** EE_UINT8 EE_button_get_B3() or EE_twrs12g128_button_get_B3()<br />
** EE_UINT8 EE_button_get_B4() or EE_twrs12g128_button_get_B4()<br />
<br />
= Examples =<br />
<br />
* The examples and tests are available in this folders:<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12xs/ S12XS examples]<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12g/ S12G examples]<br />
* OIL example:<br />
CPU test_application {<br />
OS EE {<br />
EE_OPT = "__ASSERT__"; // to use assertion mechanism<br />
EE_OPT = "DEBUG"; // to include debug info<br />
EE_OPT = "__CODEWARRIOR__"; // to use CODEWARRIOR compiler otherwise COSMIC compiler will be used.<br />
EE_OPT = "CW_EVAL_VERSION"; // If the Codewarrior compiler license is expired use this <br />
// option to avoid syntax errors during the compilation.<br />
CFLAGS = "-D__FAR_DATA"; // Options for the C compiler (refer to the compiler manual)<br />
ASFLAGS = ""; // Options for the assembler (refer to the assembler manual)<br />
LDFLAGS = "-addansibi.lib"; // Options for the linker (refer to the linker manual)<br />
CPU_DATA = MC9S12 { // CPU section<br />
APP_SRC = "code.c"; // Specify source files in this section...<br />
APP_SRC = "Vectors.c";<br />
APP_SRC = "CPU12ISRs.c";<br />
APP_SRC = "Start12.c";<br />
MULTI_STACK = FALSE;<br />
};<br />
MCU_DATA = MC9S12 { // MCU section<br />
MODEL = CUSTOM{ // Allowed values for S12 are: MC9S12G128, MC9S12XS128, CUSTOM<br />
// MC9S12G128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12G128.prm (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12g128.h (from the CW compiler installation directory)<br />
// Codewarrior SRC: mc9s12g128.c (from the CW compiler installation directory)<br />
// No Cosmic support for MC9S12G128 <br />
// MC9S12XS128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12XS128.prm (in ee\pkg\mcu\hs12xs)<br />
// Cosmic Linker script: MC9S12XS128.lkf (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12xs128.h (from the compiler installation directory)<br />
// Cosmic Header: ioxs256.h (from the compiler installation directory)<br />
// Codewarrior SRC: mc9s12xs128.c (from the compiler installation directory)<br />
// Cosmic SRC: nothing<br />
// CUSTOM model can be used to change default settings.<br />
MODEL = "MC9S12G128"; // Device model<br />
LINKERSCRIPT = "../mc9s12g128.prm"; // User linker script. If this field is void, a default linker script will be used.<br />
INCLUDE_H = "mc9s12g128.h"; // Header from user or compiler folder. <br />
INCLUDE_C = "mc9s12g128.c"; // Registers definition file from user or compiler folder.<br />
INCLUDE_S = ""; // ASM file for startup if needed.<br />
};<br />
TIMER = TRUE; // This options enables timer driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_TIMER__, __USE_PIT__<br />
// MC9S12G128: __USE_TIMER__ <br />
SERIAL = TRUE; // This options enables serial interface driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_SCI__<br />
// MC9S12G128: __USE_SCI__<br />
};<br />
STATUS = EXTENDED; // Kernel configuration <br />
STARTUPHOOK = FALSE;<br />
ERRORHOOK = FALSE;<br />
SHUTDOWNHOOK = FALSE;<br />
PRETASKHOOK = FALSE;<br />
POSTTASKHOOK = FALSE;<br />
USEGETSERVICEID = FALSE;<br />
USEPARAMETERACCESS = FALSE;<br />
USERESSCHEDULER = TRUE;<br />
KERNEL_TYPE = BCC1; // Kernel type <br />
};<br />
/* Here you can specify tasks, alarms, events, counters, ... */<br />
TASK Task1 {<br />
PRIORITY = 1;<br />
ACTIVATION = 1;<br />
SCHEDULE = FULL;<br />
AUTOSTART = TRUE;<br />
STACK = SHARED;<br />
};<br />
COUNTER Counter1 {<br />
MINCYCLE = 2;<br />
MAXALLOWEDVALUE = 16 ;<br />
TICKSPERBASE = 1;<br />
};<br />
ALARM Alarm1 {<br />
COUNTER = "Counter1";<br />
ACTION = ACTIVATETASK { TASK = "Task1"; };<br />
AUTOSTART = FALSE;<br />
};<br />
};<br />
<br />
= Download and install =<br />
<br />
RT-Druid and Erika Enterprise RTOS (version 1.6.0), for Microsoft Windows, can be freely downloaded from the following web address:<br />
* [http://download.tuxfamily.org/erika/webdownload/eeb_gpl/EE_160_Win.zip EE_160_Win.zip]<br />
<br />
Once downloaded, extract all the files contained in it and copy the folder named ''eclipse'' in your preferred directory on your PC (a recommended path is: C:\Evidence\).<br />
Now, launch the program by double-clicking on the executable ''eclipse.exe''inside the ''C:\Evidence\eclipse'' folder and choose the path of your workspace.<br />
The workspace is the default working directory in which the projects will be created. <br />
<br />
<br />
If you want to download only a selected revision of the kernel, open the Cygwin shell and get an anonymous SVN checkout typing this command:<br />
svn co svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/ee/trunk/ee -r number_of_revision<br />
<br />
Note: <br />
Cygwin can be downloaded from this web site: http://www.cygwin.com/ <br />
To use SVN, the Cygwin SVN package must to be installed using the Cygwin Setup utility.<br />
<br />
<br />
To update your RT-DRUID version:<br />
* Open the “Help” menu item and selecting “Install New Software” (see image below).<br />
[[image:install_new_sw.PNG|center|100px]]<br />
* Then add, for example, the following path: [http://download.tuxfamily.org/erika/webdownload/rtdruid_160_nb/]<br />
* To add a new web address, clicking on “Add” and write the desired address in the filed “Location” (see image below).<br />
[[image:add_web_address.PNG|center|100px]]<br />
* Select all the plugins and click on the “Next” button. Then click again on “Next”, read the conditions and ''in case'' accept them by clicking on the “Finish” button.<br />
* Wait for the completion of the update and restart before using the software.<br />
<br />
<br />
'''Warnings and recommendations''' <br />
* For a fast installation deselect ''Contact all update sites during install to find required software''.<br />
* The revision '''1543''' of '''RT-Druid''' and '''Erika''' has been tested on the MODISTARC testcase, so this version is recommended.<br />
* However, the new Erika HCS12 package can work also with the previous versions of RT-Druid.<br />
<br />
= How to build a project in RT-DRUID =<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12XS]]<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12G]]<br />
* [[Tutorial: S12XS - First installation and application compilation on Windows]]<br />
* [[OIL example for Freescale S12]]<br />
<br />
= How to run MODISTARC regression tests =<br />
* [[A brief description on how to run MODISTARC regression tests for Freescale S12XS]]<br />
<br />
<br />
[[Category:Supported Devices]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Freescale_S12Freescale S122011-12-13T10:35:02Z<p>Erikadds: /* Download and install */</p>
<hr />
<div>= Freescale S12 support =<br />
ERIKA Enterprise supports Freescale HCS12 microcontrollers. <br />
The support for RT-Druid is now available .<br><br />
The HCS12 support includes: <br />
# support for '''COSMIC''' compiler (only for HCS12XS, since Erika release 1.5.0) <br />
# support for '''CODEWARRIOR CWS12v5.1''' compiler (since Erika release 1.6.0).<br />
# support for single and multi stack configurations.<br />
# ISR interrupt supported.<br />
# support for Freescale HIWAVE Debugger.<br />
<br />
* '''Supported compiler'''<br />
** COSMIC C cross compiler and ELF module generation for debugging information.<br />
** CODEWARRIOR CWS12v5.1 compiler and ELF module generation for debugging information.<br />
::* CODEWARRIOR compiler is enabled adding this option in the conf.oil file:<br />
EE_OPT = "__CODEWARRIOR__";<br />
::* If the compiler evaluation license is expired, you may have to add also this option to avoid syntax errors during the compilation:<br />
EE_OPT = "CW_EVAL_VERSION"; <br />
* '''Mode of operation'''<br />
** ''Mono-stack'': The Monostack configuration of the ERIKA Kernel models the fact that all tasks and ISRs in the system share the same stack.<br />
** ''Multi-stack'': Every thread can have its private stack, or it can share it with other threads. <br />
<br />
* '''Handling of paging registers'''<br />
:The compiler supports bank switching for code and data, using the internal window mechanism provided by the HCS12 processor.<br />
:Bank switching mechanism delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.<br />
:Bank switching is supported via:<br />
:- @far type qualifier to describe a function relocated in a different bank. Calling such a function implies a special calling <br />
:sequence, and a special return sequence. Such a function has to be defined @far and referenced as @far in all the files using <br />
:it. The COSMIC compiler also provides a specific option +modf to automatically consider all the functions to be @far. The @far type <br />
:modifier is also used to declared variables allocated in a data bank.<br />
:- Linker options are required to ensure proper physical and logical addresses computations. The linker is also able to <br />
:automatically fill banks without any need to take care of the page boundaries.<br />
<br />
= CPUs =<br />
* '''S12 Hardware Abstraction Layer''' (since Erika revision 1531): S12 HAL now integrates the Erika HAL common files (see [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/cpu/common/ 'pkg/cpu/common'] folder and [http://erika.tuxfamily.org/wiki/index.php?title=Common_files_for_the_HAL Common_files_for_the_HAL] for further info). This feature simplifies future extensions for other S12 devices and ensures greater code stability against changes to the kernel code.<br />
* '''Nesting of interrupts''':<br />
** ''MC9s12XS128'': The IPL bits allow the nesting of interrupts, blocking interrupts of an equal or lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.<br />
** ''MC9S12G128'': <pre style="color:red">WARNING: MC9S12G128 doesn't support IPL mechanism.</pre> To enable the nesting of interrupts in the code, the user should clear I bit (in the CCR register) inside the interrupt service routine and after the peripheral interrupt flag has been cleared. If the I bit is cleared before the peripheral interrupt flag has been cleared the CPU restarts the interrupt creating an infinite loop. For this reason I-bit cannot be cleared inside Erika HAL files and this task is left to the user. To enable the compilation of the code for the nesting of interrupts the symbol<br />
__ALLOW_NESTED_IRQ__<br />
must be defined.<br />
Note: If the kernel type is FP the nesting of the interrupts can be enabled in this way:<br />
KERNEL_TYPE = FP{<br />
NESTED_IRQ = TRUE;<br />
}; <br />
otherwise the default case is FALSE and the nesting of the interrupts is disabled.<br />
<br />
= MCUs =<br />
<br />
* The MCUs currently supported are the following:<br />
** ''Freescale'' '''MC9S12XS128'''<br />
** ''Freescale'' '''MC9S12G128'''<br />
<br />
* List of functions:<br />
** ''Periodic interrupt timer''<br />
*** void EE_pit0_init( unsigned char pitmtld0, unsigned char pitld0, unsigned char prio ); // To init PIT0<br />
*** void EE_pit0_close( void ); // To close PIT0<br />
*** void EE_pit0_clear_ISRflag( void ); // To clean PIT0 ISR flag <br />
** ''Serial communication interface''<br />
*** void EE_sci_open(unsigned char sci_num, unsigned long int baudrate); // Open the serial interface. Requires: EE_set_peripheral_frequency_mhz(f_mhz) <br />
*** void EE_sci_close(unsigned char sci_num); // To close the serial interface<br />
*** Bool EE_sci_send_byte(unsigned char sci_num, unsigned char buffer); // To send a byte<br />
*** Bool EE_sci_send_string(unsigned char sci_num, const char* s, unsigned int num); // to send a string<br />
*** Bool EE_sci_send_bytes(unsigned char sci_num, char* v, unsigned int num); // To send a vector of bytes<br />
*** Bool EE_sci_get_byte(unsigned char sci_num, unsigned char *buffer); // to get a byte<br />
*** Bool EE_sci_getcheck(unsigned char sci_num); // to check the serial reception of a byte<br />
** ''Timer''<br />
*** int EE_timer_init_us(EE_UINT16 tim_id, EE_UINT32 period_us, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** int EE_timer_init_ms(EE_UINT16 tim_id, EE_UINT16 period_ms, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** void EE_timer_start() // start timer<br />
*** void EE_timer_stop() // stop timer<br />
*** void EE_timer_reset() // reset timer<br />
*** void EE_timer_clear_ISRflag(EE_UINT16 tim_id) // clear interrrupt flag<br />
*** EE_UINT16 EE_timer_get_counter() // get counter<br />
*** void EE_timer_enable_ISR(EE_UINT16 tim_id, EE_UINT8 isr_mode) // enable IRQ<br />
** void EE_timer_disable_ISR(EE_UINT16 tim_id) // disable IRQ<br />
<br />
= Boards =<br />
<br />
* The boards currently supported are the following:<br />
** ''SofTec Microsystems'' '''DEMO9S12XSFAME''' demo board.<br />
** ''Freescale Axiom'' '''TWRS12G128''' evaluation board.<br />
<br />
<br />
* '''DEMO9S12XSFAME''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/hs12xs_demo9s12xsfame/ demo9s12xsfame])<br />
** void EE_demo9s12xsfame_leds_init(void); // To configure the leds port <br />
** void EE_demo9s12xsfame_leds( EE_UINT8 data ); // To set the led port vaules <br />
** void EE_demo9s12xsfame_led_0_on(void); // To turn on LED0<br />
** void EE_demo9s12xsfame_led_0_off(void); // To turn off LED0<br />
** void EE_demo9s12xsfame_led_1_on(void); // To turn on LED1<br />
** void EE_demo9s12xsfame_led_1_off(void); // To turn off LED1<br />
** void EE_demo9s12xsfame_led_2_on(void); // To turn on LED2<br />
** void EE_demo9s12xsfame_led_2_off(void); // To turn off LED2<br />
** void EE_demo9s12xsfame_led_3_on(void); // To turn on LED3<br />
** void EE_demo9s12xsfame_led_3_off(void); // To turn off LED3<br />
** void EE_demo9s12xsfame_leds_on(void); // To turn on all the leds<br />
** void EE_demo9s12xsfame_leds_off(void); // To turn off all the leds<br />
** void EE_demo9s12xsfame_buttons_init( EE_UINT8 bx, EE_UINT8 prio ); // To init the buttons port<br />
** void EE_demo9s12xsfame_buttons_close( void ); // To reset the buttons port<br />
** void EE_demo9s12xsfame_buttons_disable_interrupts( EE_UINT8 bx ); // To disable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_enable_interrupts( EE_UINT8 bx ); // To enable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_clear_ISRflag( EE_UINT8 bx ); // To clear button ISR flag<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B0( void ); // To get the BUTTON0 value<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B1( void ); // To get the BUTTON1 value<br />
** void EE_demo9s12xsfame_adc_init( unsigned char res, unsigned char numconvseq ); // To init ADC<br />
** void EE_demo9s12xsfame_adc_convert( void ); // To start conversion<br />
** unsigned int EE_demo9s12xsfame_adc_getvalue( unsigned int adcch ); // To get a value<br />
** void EE_demo9s12xsfame_adc_close( void ); // To close ADC<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_light( void ); // To get light sensor value<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_pot( void ); // To get potentiometer value<br />
<br />
<br />
* '''TWRS12G128''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/twrs12g128/ twrs12g128])<br />
** void EE_leds_init() or EE_twrs12g128_leds_init()<br />
** void EE_leds(EE_UINT8 data) or EE_twrs12g128_leds(EE_UINT8 data)<br />
** void EE_led_1_on() or EE_twrs12g128_led_1_on() <br />
** void EE_led_1_off() or EE_twrs12g128_led_1_off() <br />
** void EE_led_2_on() or EE_twrs12g128_led_2_on() <br />
** void EE_led_2_off() or EE_twrs12g128_led_2_off() <br />
** void EE_led_3_on() or EE_twrs12g128_led_3_on() <br />
** void EE_led_3_off() or EE_twrs12g128_led_3_off() <br />
** void EE_led_4_on() or EE_twrs12g128_led_4_on() <br />
** void EE_led_4_off() or EE_twrs12g128_led_4_off()<br />
** void EE_led_1_toggle() or EE_twrs12g128_led_1_toggle()<br />
** void EE_led_2_toggle() or EE_twrs12g128_led_2_toggle()<br />
** void EE_led_3_toggle() or EE_twrs12g128_led_3_toggle()<br />
** void EE_led_4_toggle() or EE_twrs12g128_led_4_toggle()<br />
** void EE_leds_on() or EE_twrs12g128_leds_on() <br />
** void EE_leds_off() or EE_twrs12g128_leds_off() <br />
** void EE_buttons_init(EE_UINT8 bx) or EE_twrs12g128_buttons_init(EE_UINT8 bx)<br />
** void EE_buttons_close or EE_twrs12g128_buttons_close()<br />
** EE_UINT8 EE_button_get_B1() or EE_twrs12g128_button_get_B1()<br />
** EE_UINT8 EE_button_get_B2() or EE_twrs12g128_button_get_B2()<br />
** EE_UINT8 EE_button_get_B3() or EE_twrs12g128_button_get_B3()<br />
** EE_UINT8 EE_button_get_B4() or EE_twrs12g128_button_get_B4()<br />
<br />
= Examples =<br />
<br />
* The examples and tests are available in this folders:<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12xs/ S12XS examples]<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12g/ S12G examples]<br />
* OIL example:<br />
CPU test_application {<br />
OS EE {<br />
EE_OPT = "__ASSERT__"; // to use assertion mechanism<br />
EE_OPT = "DEBUG"; // to include debug info<br />
EE_OPT = "__CODEWARRIOR__"; // to use CODEWARRIOR compiler otherwise COSMIC compiler will be used.<br />
EE_OPT = "CW_EVAL_VERSION"; // If the Codewarrior compiler license is expired use this <br />
// option to avoid syntax errors during the compilation.<br />
CFLAGS = "-D__FAR_DATA"; // Options for the C compiler (refer to the compiler manual)<br />
ASFLAGS = ""; // Options for the assembler (refer to the assembler manual)<br />
LDFLAGS = "-addansibi.lib"; // Options for the linker (refer to the linker manual)<br />
CPU_DATA = MC9S12 { // CPU section<br />
APP_SRC = "code.c"; // Specify source files in this section...<br />
APP_SRC = "Vectors.c";<br />
APP_SRC = "CPU12ISRs.c";<br />
APP_SRC = "Start12.c";<br />
MULTI_STACK = FALSE;<br />
};<br />
MCU_DATA = MC9S12 { // MCU section<br />
MODEL = CUSTOM{ // Allowed values for S12 are: MC9S12G128, MC9S12XS128, CUSTOM<br />
// MC9S12G128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12G128.prm (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12g128.h (from the CW compiler installation directory)<br />
// Codewarrior SRC: mc9s12g128.c (from the CW compiler installation directory)<br />
// No Cosmic support for MC9S12G128 <br />
// MC9S12XS128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12XS128.prm (in ee\pkg\mcu\hs12xs)<br />
// Cosmic Linker script: MC9S12XS128.lkf (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12xs128.h (from the compiler installation directory)<br />
// Cosmic Header: ioxs256.h (from the compiler installation directory)<br />
// Codewarrior SRC: mc9s12xs128.c (from the compiler installation directory)<br />
// Cosmic SRC: nothing<br />
// CUSTOM model can be used to change default settings.<br />
MODEL = "MC9S12G128"; // Device model<br />
LINKERSCRIPT = "../mc9s12g128.prm"; // User linker script. If this field is void, a default linker script will be used.<br />
INCLUDE_H = "mc9s12g128.h"; // Header from user or compiler folder. <br />
INCLUDE_C = "mc9s12g128.c"; // Registers definition file from user or compiler folder.<br />
INCLUDE_S = ""; // ASM file for startup if needed.<br />
};<br />
TIMER = TRUE; // This options enables timer driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_TIMER__, __USE_PIT__<br />
// MC9S12G128: __USE_TIMER__ <br />
SERIAL = TRUE; // This options enables serial interface driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_SCI__<br />
// MC9S12G128: __USE_SCI__<br />
};<br />
STATUS = EXTENDED; // Kernel configuration <br />
STARTUPHOOK = FALSE;<br />
ERRORHOOK = FALSE;<br />
SHUTDOWNHOOK = FALSE;<br />
PRETASKHOOK = FALSE;<br />
POSTTASKHOOK = FALSE;<br />
USEGETSERVICEID = FALSE;<br />
USEPARAMETERACCESS = FALSE;<br />
USERESSCHEDULER = TRUE;<br />
KERNEL_TYPE = BCC1; // Kernel type <br />
};<br />
/* Here you can specify tasks, alarms, events, counters, ... */<br />
TASK Task1 {<br />
PRIORITY = 1;<br />
ACTIVATION = 1;<br />
SCHEDULE = FULL;<br />
AUTOSTART = TRUE;<br />
STACK = SHARED;<br />
};<br />
COUNTER Counter1 {<br />
MINCYCLE = 2;<br />
MAXALLOWEDVALUE = 16 ;<br />
TICKSPERBASE = 1;<br />
};<br />
ALARM Alarm1 {<br />
COUNTER = "Counter1";<br />
ACTION = ACTIVATETASK { TASK = "Task1"; };<br />
AUTOSTART = FALSE;<br />
};<br />
};<br />
<br />
= Download and install =<br />
<br />
RT-Druid and Erika Enterprise RTOS (version 1.6.0), for Microsoft Windows, can be freely downloaded from the following web address:<br />
* [http://download.tuxfamily.org/erika/webdownload/eeb_gpl/EE_160_Win.zip EE_160_Win.zip]<br />
<br />
Once downloaded, extract all the files contained in it and copy the folder named ''eclipse'' in your preferred directory on your PC (a recommended path is: C:\Evidence\).<br />
Now, launch the program by double-clicking on the executable ''eclipse.exe''inside the ''C:\Evidence\eclipse'' folder and choose the path of your workspace.<br />
The workspace is the default working directory in which the projects will be created. <br />
<br />
<br />
If you want to download only a selected revision of the kernel, open the Cygwin shell and get an anonymous SVN checkout typing this command:<br />
svn co svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/ee/trunk/ee -r number_of_revision<br />
<br />
Note: <br />
Cygwin can be downloaded from this web site: http://www.cygwin.com/ <br />
To use SVN, the Cygwin SVN package must to be installed using the Cygwin Setup utility.<br />
<br />
<br />
To update your RT-DRUID version:<br />
* Open the “Help” menu item and selecting “Install New Software” (see image below).<br />
[[image:install_new_sw.PNG|center|100px]]<br />
* Then add, for example, the following path: [http://download.tuxfamily.org/erika/webdownload/rtdruid_160_nb/]<br />
* To add a new web address, clicking on “Add” and write the desired address in the filed “Location” (see image below).<br />
[[image:add_web_address.PNG|center|100px]]<br />
* Select all the plugins and click on the “Next” button. Then click again on “Next”, read the conditions and ''in case'' accept them by clicking on the “Finish” button.<br />
* Wait for the completion of the update and restart before using the software.<br />
<br />
<br />
'''Warnings and recommendations''' <br />
* For a fast installation deselect ''Contact all update sites during install to find required software''.<br />
* The revision '''1543''' of '''RT-Druid''' and '''Erika''' has been tested on the MODISTARC testcase, so this version is recommended.<br />
* However, the new Erika HCS12 package can work also with the previous versions of RT-Druid.<br />
<br />
= How to build a project in RT-DRUID =<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12XS]]<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12G]]<br />
<br />
= How to run MODISTARC regression tests =<br />
* [[A brief description on how to run MODISTARC regression tests for Freescale S12XS]]<br />
<br />
<br />
[[Category:Supported Devices]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=Freescale_S12Freescale S122011-12-13T10:09:18Z<p>Erikadds: /* Download and install */</p>
<hr />
<div>= Freescale S12 support =<br />
ERIKA Enterprise supports Freescale HCS12 microcontrollers. <br />
The support for RT-Druid is now available .<br><br />
The HCS12 support includes: <br />
# support for '''COSMIC''' compiler (only for HCS12XS, since Erika release 1.5.0) <br />
# support for '''CODEWARRIOR CWS12v5.1''' compiler (since Erika release 1.6.0).<br />
# support for single and multi stack configurations.<br />
# ISR interrupt supported.<br />
# support for Freescale HIWAVE Debugger.<br />
<br />
* '''Supported compiler'''<br />
** COSMIC C cross compiler and ELF module generation for debugging information.<br />
** CODEWARRIOR CWS12v5.1 compiler and ELF module generation for debugging information.<br />
::* CODEWARRIOR compiler is enabled adding this option in the conf.oil file:<br />
EE_OPT = "__CODEWARRIOR__";<br />
::* If the compiler evaluation license is expired, you may have to add also this option to avoid syntax errors during the compilation:<br />
EE_OPT = "CW_EVAL_VERSION"; <br />
* '''Mode of operation'''<br />
** ''Mono-stack'': The Monostack configuration of the ERIKA Kernel models the fact that all tasks and ISRs in the system share the same stack.<br />
** ''Multi-stack'': Every thread can have its private stack, or it can share it with other threads. <br />
<br />
* '''Handling of paging registers'''<br />
:The compiler supports bank switching for code and data, using the internal window mechanism provided by the HCS12 processor.<br />
:Bank switching mechanism delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.<br />
:Bank switching is supported via:<br />
:- @far type qualifier to describe a function relocated in a different bank. Calling such a function implies a special calling <br />
:sequence, and a special return sequence. Such a function has to be defined @far and referenced as @far in all the files using <br />
:it. The COSMIC compiler also provides a specific option +modf to automatically consider all the functions to be @far. The @far type <br />
:modifier is also used to declared variables allocated in a data bank.<br />
:- Linker options are required to ensure proper physical and logical addresses computations. The linker is also able to <br />
:automatically fill banks without any need to take care of the page boundaries.<br />
<br />
= CPUs =<br />
* '''S12 Hardware Abstraction Layer''' (since Erika revision 1531): S12 HAL now integrates the Erika HAL common files (see [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/cpu/common/ 'pkg/cpu/common'] folder and [http://erika.tuxfamily.org/wiki/index.php?title=Common_files_for_the_HAL Common_files_for_the_HAL] for further info). This feature simplifies future extensions for other S12 devices and ensures greater code stability against changes to the kernel code.<br />
* '''Nesting of interrupts''':<br />
** ''MC9s12XS128'': The IPL bits allow the nesting of interrupts, blocking interrupts of an equal or lower priority. The current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the Priority Level of the highest priority active interrupt request channel. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.<br />
** ''MC9S12G128'': <pre style="color:red">WARNING: MC9S12G128 doesn't support IPL mechanism.</pre> To enable the nesting of interrupts in the code, the user should clear I bit (in the CCR register) inside the interrupt service routine and after the peripheral interrupt flag has been cleared. If the I bit is cleared before the peripheral interrupt flag has been cleared the CPU restarts the interrupt creating an infinite loop. For this reason I-bit cannot be cleared inside Erika HAL files and this task is left to the user. To enable the compilation of the code for the nesting of interrupts the symbol<br />
__ALLOW_NESTED_IRQ__<br />
must be defined.<br />
Note: If the kernel type is FP the nesting of the interrupts can be enabled in this way:<br />
KERNEL_TYPE = FP{<br />
NESTED_IRQ = TRUE;<br />
}; <br />
otherwise the default case is FALSE and the nesting of the interrupts is disabled.<br />
<br />
= MCUs =<br />
<br />
* The MCUs currently supported are the following:<br />
** ''Freescale'' '''MC9S12XS128'''<br />
** ''Freescale'' '''MC9S12G128'''<br />
<br />
* List of functions:<br />
** ''Periodic interrupt timer''<br />
*** void EE_pit0_init( unsigned char pitmtld0, unsigned char pitld0, unsigned char prio ); // To init PIT0<br />
*** void EE_pit0_close( void ); // To close PIT0<br />
*** void EE_pit0_clear_ISRflag( void ); // To clean PIT0 ISR flag <br />
** ''Serial communication interface''<br />
*** void EE_sci_open(unsigned char sci_num, unsigned long int baudrate); // Open the serial interface. Requires: EE_set_peripheral_frequency_mhz(f_mhz) <br />
*** void EE_sci_close(unsigned char sci_num); // To close the serial interface<br />
*** Bool EE_sci_send_byte(unsigned char sci_num, unsigned char buffer); // To send a byte<br />
*** Bool EE_sci_send_string(unsigned char sci_num, const char* s, unsigned int num); // to send a string<br />
*** Bool EE_sci_send_bytes(unsigned char sci_num, char* v, unsigned int num); // To send a vector of bytes<br />
*** Bool EE_sci_get_byte(unsigned char sci_num, unsigned char *buffer); // to get a byte<br />
*** Bool EE_sci_getcheck(unsigned char sci_num); // to check the serial reception of a byte<br />
** ''Timer''<br />
*** int EE_timer_init_us(EE_UINT16 tim_id, EE_UINT32 period_us, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** int EE_timer_init_ms(EE_UINT16 tim_id, EE_UINT16 period_ms, EE_UINT8 isr_mode) // init timer. Requires: EE_set_peripheral_frequency_mhz(f_mhz)<br />
*** void EE_timer_start() // start timer<br />
*** void EE_timer_stop() // stop timer<br />
*** void EE_timer_reset() // reset timer<br />
*** void EE_timer_clear_ISRflag(EE_UINT16 tim_id) // clear interrrupt flag<br />
*** EE_UINT16 EE_timer_get_counter() // get counter<br />
*** void EE_timer_enable_ISR(EE_UINT16 tim_id, EE_UINT8 isr_mode) // enable IRQ<br />
** void EE_timer_disable_ISR(EE_UINT16 tim_id) // disable IRQ<br />
<br />
= Boards =<br />
<br />
* The boards currently supported are the following:<br />
** ''SofTec Microsystems'' '''DEMO9S12XSFAME''' demo board.<br />
** ''Freescale Axiom'' '''TWRS12G128''' evaluation board.<br />
<br />
<br />
* '''DEMO9S12XSFAME''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/hs12xs_demo9s12xsfame/ demo9s12xsfame])<br />
** void EE_demo9s12xsfame_leds_init(void); // To configure the leds port <br />
** void EE_demo9s12xsfame_leds( EE_UINT8 data ); // To set the led port vaules <br />
** void EE_demo9s12xsfame_led_0_on(void); // To turn on LED0<br />
** void EE_demo9s12xsfame_led_0_off(void); // To turn off LED0<br />
** void EE_demo9s12xsfame_led_1_on(void); // To turn on LED1<br />
** void EE_demo9s12xsfame_led_1_off(void); // To turn off LED1<br />
** void EE_demo9s12xsfame_led_2_on(void); // To turn on LED2<br />
** void EE_demo9s12xsfame_led_2_off(void); // To turn off LED2<br />
** void EE_demo9s12xsfame_led_3_on(void); // To turn on LED3<br />
** void EE_demo9s12xsfame_led_3_off(void); // To turn off LED3<br />
** void EE_demo9s12xsfame_leds_on(void); // To turn on all the leds<br />
** void EE_demo9s12xsfame_leds_off(void); // To turn off all the leds<br />
** void EE_demo9s12xsfame_buttons_init( EE_UINT8 bx, EE_UINT8 prio ); // To init the buttons port<br />
** void EE_demo9s12xsfame_buttons_close( void ); // To reset the buttons port<br />
** void EE_demo9s12xsfame_buttons_disable_interrupts( EE_UINT8 bx ); // To disable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_enable_interrupts( EE_UINT8 bx ); // To enable interrupt related to the buttons<br />
** void EE_demo9s12xsfame_buttons_clear_ISRflag( EE_UINT8 bx ); // To clear button ISR flag<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B0( void ); // To get the BUTTON0 value<br />
** EE_UINT8 EE_demo9s12xsfame_button_get_B1( void ); // To get the BUTTON1 value<br />
** void EE_demo9s12xsfame_adc_init( unsigned char res, unsigned char numconvseq ); // To init ADC<br />
** void EE_demo9s12xsfame_adc_convert( void ); // To start conversion<br />
** unsigned int EE_demo9s12xsfame_adc_getvalue( unsigned int adcch ); // To get a value<br />
** void EE_demo9s12xsfame_adc_close( void ); // To close ADC<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_light( void ); // To get light sensor value<br />
** EE_UINT16 EE_demo9s12xsfame_analog_get_pot( void ); // To get potentiometer value<br />
<br />
<br />
* '''TWRS12G128''' List of functions (refer to [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/pkg/board/twrs12g128/ twrs12g128])<br />
** void EE_leds_init() or EE_twrs12g128_leds_init()<br />
** void EE_leds(EE_UINT8 data) or EE_twrs12g128_leds(EE_UINT8 data)<br />
** void EE_led_1_on() or EE_twrs12g128_led_1_on() <br />
** void EE_led_1_off() or EE_twrs12g128_led_1_off() <br />
** void EE_led_2_on() or EE_twrs12g128_led_2_on() <br />
** void EE_led_2_off() or EE_twrs12g128_led_2_off() <br />
** void EE_led_3_on() or EE_twrs12g128_led_3_on() <br />
** void EE_led_3_off() or EE_twrs12g128_led_3_off() <br />
** void EE_led_4_on() or EE_twrs12g128_led_4_on() <br />
** void EE_led_4_off() or EE_twrs12g128_led_4_off()<br />
** void EE_led_1_toggle() or EE_twrs12g128_led_1_toggle()<br />
** void EE_led_2_toggle() or EE_twrs12g128_led_2_toggle()<br />
** void EE_led_3_toggle() or EE_twrs12g128_led_3_toggle()<br />
** void EE_led_4_toggle() or EE_twrs12g128_led_4_toggle()<br />
** void EE_leds_on() or EE_twrs12g128_leds_on() <br />
** void EE_leds_off() or EE_twrs12g128_leds_off() <br />
** void EE_buttons_init(EE_UINT8 bx) or EE_twrs12g128_buttons_init(EE_UINT8 bx)<br />
** void EE_buttons_close or EE_twrs12g128_buttons_close()<br />
** EE_UINT8 EE_button_get_B1() or EE_twrs12g128_button_get_B1()<br />
** EE_UINT8 EE_button_get_B2() or EE_twrs12g128_button_get_B2()<br />
** EE_UINT8 EE_button_get_B3() or EE_twrs12g128_button_get_B3()<br />
** EE_UINT8 EE_button_get_B4() or EE_twrs12g128_button_get_B4()<br />
<br />
= Examples =<br />
<br />
* The examples and tests are available in this folders:<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12xs/ S12XS examples]<br />
** [http://svn.tuxfamily.org/viewvc.cgi/erika_erikae/repos/ee/trunk/ee/examples/s12g/ S12G examples]<br />
* OIL example:<br />
CPU test_application {<br />
OS EE {<br />
EE_OPT = "__ASSERT__"; // to use assertion mechanism<br />
EE_OPT = "DEBUG"; // to include debug info<br />
EE_OPT = "__CODEWARRIOR__"; // to use CODEWARRIOR compiler otherwise COSMIC compiler will be used.<br />
EE_OPT = "CW_EVAL_VERSION"; // If the Codewarrior compiler license is expired use this <br />
// option to avoid syntax errors during the compilation.<br />
CFLAGS = "-D__FAR_DATA"; // Options for the C compiler (refer to the compiler manual)<br />
ASFLAGS = ""; // Options for the assembler (refer to the assembler manual)<br />
LDFLAGS = "-addansibi.lib"; // Options for the linker (refer to the linker manual)<br />
CPU_DATA = MC9S12 { // CPU section<br />
APP_SRC = "code.c"; // Specify source files in this section...<br />
APP_SRC = "Vectors.c";<br />
APP_SRC = "CPU12ISRs.c";<br />
APP_SRC = "Start12.c";<br />
MULTI_STACK = FALSE;<br />
};<br />
MCU_DATA = MC9S12 { // MCU section<br />
MODEL = CUSTOM{ // Allowed values for S12 are: MC9S12G128, MC9S12XS128, CUSTOM<br />
// MC9S12G128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12G128.prm (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12g128.h (from the CW compiler installation directory)<br />
// Codewarrior SRC: mc9s12g128.c (from the CW compiler installation directory)<br />
// No Cosmic support for MC9S12G128 <br />
// MC9S12XS128 model uses these default settings:<br />
// Codewarrior Linker script: MC9S12XS128.prm (in ee\pkg\mcu\hs12xs)<br />
// Cosmic Linker script: MC9S12XS128.lkf (in ee\pkg\mcu\hs12xs)<br />
// Codewarrior Header: mc9s12xs128.h (from the compiler installation directory)<br />
// Cosmic Header: ioxs256.h (from the compiler installation directory)<br />
// Codewarrior SRC: mc9s12xs128.c (from the compiler installation directory)<br />
// Cosmic SRC: nothing<br />
// CUSTOM model can be used to change default settings.<br />
MODEL = "MC9S12G128"; // Device model<br />
LINKERSCRIPT = "../mc9s12g128.prm"; // User linker script. If this field is void, a default linker script will be used.<br />
INCLUDE_H = "mc9s12g128.h"; // Header from user or compiler folder. <br />
INCLUDE_C = "mc9s12g128.c"; // Registers definition file from user or compiler folder.<br />
INCLUDE_S = ""; // ASM file for startup if needed.<br />
};<br />
TIMER = TRUE; // This options enables timer driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_TIMER__, __USE_PIT__<br />
// MC9S12G128: __USE_TIMER__ <br />
SERIAL = TRUE; // This options enables serial interface driver compilation. Equivalent options:<br />
// MC9S12XS128: __USE_SCI__<br />
// MC9S12G128: __USE_SCI__<br />
};<br />
STATUS = EXTENDED; // Kernel configuration <br />
STARTUPHOOK = FALSE;<br />
ERRORHOOK = FALSE;<br />
SHUTDOWNHOOK = FALSE;<br />
PRETASKHOOK = FALSE;<br />
POSTTASKHOOK = FALSE;<br />
USEGETSERVICEID = FALSE;<br />
USEPARAMETERACCESS = FALSE;<br />
USERESSCHEDULER = TRUE;<br />
KERNEL_TYPE = BCC1; // Kernel type <br />
};<br />
/* Here you can specify tasks, alarms, events, counters, ... */<br />
TASK Task1 {<br />
PRIORITY = 1;<br />
ACTIVATION = 1;<br />
SCHEDULE = FULL;<br />
AUTOSTART = TRUE;<br />
STACK = SHARED;<br />
};<br />
COUNTER Counter1 {<br />
MINCYCLE = 2;<br />
MAXALLOWEDVALUE = 16 ;<br />
TICKSPERBASE = 1;<br />
};<br />
ALARM Alarm1 {<br />
COUNTER = "Counter1";<br />
ACTION = ACTIVATETASK { TASK = "Task1"; };<br />
AUTOSTART = FALSE;<br />
};<br />
};<br />
<br />
= Download and install =<br />
<br />
RT-Druid and Erika Enterprise RTOS (version 1.6.0), for Microsoft Windows, can be freely downloaded from the following web address:<br />
* [http://download.tuxfamily.org/erika/webdownload/eeb_gpl/EE_160_Win.zip EE_160_Win.zip]<br />
<br />
Once downloaded, extract all the files contained in it and copy the folder named ''eclipse'' in your preferred directory on your PC (a recommended path is: C:\Evidence\).<br />
Now, launch the program by double-clicking on the executable ''eclipse.exe''inside the ''C:\Evidence\eclipse'' folder and choose the path of your workspace.<br />
The workspace is the default working directory in which the projects will be created. <br />
<br />
<br />
If you want to download only a selected revision of the kernel, open the Cygwin shell and get an anonymous SVN checkout typing this command:<br />
svn co svn://svn.tuxfamily.org/svnroot/erika/erikae/repos/ee/trunk/ee -r number_of_revision<br />
<br />
Note: <br />
Cygwin can be downloaded from this web site: http://www.cygwin.com/ <br />
To use SVN, the Cygwin SVN package must to be installed using the Cygwin Setup utility.<br />
<br />
<br />
To update your RT-DRUID version:<br />
* Open the “Help” menu item and selecting “Install New Software” (see image below).<br />
[[image:install_new_sw.PNG|center|100px]]<br />
* Then add, for example, the following path: [http://download.tuxfamily.org/erika/webdownload/rtdruid_160_nb/]<br />
* To add a new web address, clicking on “Add” and write the desired address in the filed “Location” (see image below).<br />
[[image:add_web_address.PNG|center|100px]]<br />
* Select all the plugins and click on the “Next” button. Then click again on “Next”, read the conditions and ''in case'' accept them by clicking on the “Finish” button.<br />
* Wait for the completion of the update and restart before using the software.<br />
<br />
<br />
'''Warnings and recommendations''' <br />
* For a fast installation deselect ''Contact all update sites during install to find required software''.<br />
* '''RT-Druid version 1276''' and '''Erika r1543''' has been tested using MODISTARC testcase, so this versions are recommended.<br />
* However, the new Erika HCS12 package can work also with the previous versions of RT-Druid.<br />
<br />
= How to build a project in RT-DRUID =<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12XS]]<br />
* [[A quick tutorial on how to create, compile and debug an application for Freescale S12G]]<br />
<br />
= How to run MODISTARC regression tests =<br />
* [[A brief description on how to run MODISTARC regression tests for Freescale S12XS]]<br />
<br />
<br />
[[Category:Supported Devices]]</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=A_quick_tutorial_on_how_to_create,_compile_and_debug_an_application_for_Freescale_S12GA quick tutorial on how to create, compile and debug an application for Freescale S12G2011-12-12T17:33:32Z<p>Erikadds: </p>
<hr />
<div>Requirements: <br />
* Install the Freescale CodeWarrior IDE and the compiler '''CWS12v5.1'''<br />
** The Windows version of the IDE (that ocntains the compiler) can be downloaded from the following site (please note that the site requires registration): [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=CW-SUITE-SPECIAL&fpsp=1&tab=Design_Tools_Tab HCS12_CODEWARRIOR_V5.1]<br />
** Install the software in your desired location (every path without blank spaces is a recommended path, for example: ''C:\Programmi\Freescale\CWS12v5.1'').<br />
* Create a project for RT-Druid. <br />
** First enter the compiler path in RT-Druid. In the menu at the top, under ''Windows - Preferences - RT-Druid - Oil - Freescale S12'', enter the path where you installed the compiler as shown in the figure.<br />
[[image:compiler_preferences.PNG|center|300px]]<br />
* Then, select ''File - New - RT_Druid ILO and C / C + + project'' to create a new project.<br />
[[image:new_s12g_project.PNG|center|300px]]<br />
* Enter the name of the project (for example: ''s12_cw_task_demo'') and click on ''Next'' to specify a template.<br />
[[image:project_name.PNG|center|300px]]<br />
* Choose the ''Monostack TASK demo'' as shown in the figure and click on the ''Finish'' button.<br />
[[image:task_demo.PNG|center|300px]]<br />
* To use a selected revision of the kernel for project building, right-click on the project name and open the ''Properties'' window. Then select ''Erika files location'' and click to ''Configure workspace Settings'' to set the EE kernel location path for the IDE or choose another option.<br />
[[image:ee_path.PNG|center|300px]]<br />
* Now you can compile all the files of the project. To do this, simply right-click on the project name and select ''Build Project''.<br />
[[image:build_s12g.PNG|center|300px]]<br />
* If the compilation has been successfully completed the executable file, named “s12.elf”, should be present inside the Debug folder in the project tree.<br />
[[image:build_success.PNG|center|300px]]<br />
* Execute the application on the S12G micro-controller. The USB drivers for the '''TWRS12G128''' board should be already installed, otherwise follow the installation procedure described in the user manual of the board. Move the power jumpers in the right position and connect the board with the USB cable (for more info see the manual of the board). Then connect the board and your PC using a serial communication cable (please note that you may need a USB-serial converter if your PC hasn't a DB9 connector).<br />
** Copy the project path from the project properties as shown in the figure (the project path is needed to upload the executable file ''s12.elf'' in the debugger).<br />
[[image:project_path.PNG|center|300px]]<br />
* Open the Freescale debugger named HIWAVE, launching the executable “hiwave.exe” located in the “Prog” folder under the installation directory of the compiler (for example: C:\Programmi\Freescale\CWS12v5.1\Prog).<br />
[[image:hiwave.PNG|center|300px]]<br />
* Board selection. Under the menu “Component” select ''Set Connection''. In the menu choose ''HC12'', ''P&E Multilink/Cyclone Pro'' in the combo boxes and click OK.<br />
[[image:pe.PNG|center|300px]]<br />
* From the HC12MultilinkCyclonePro menu, choose ''Load ...'' and upload the executable file ''s12.elf'' located in the Debug folder inside the project. <br />
Check the box ''Automatically erase and program into FLASH and EEPROM'' and click ''Open'' (see image below).<br />
[[image:hiwave_s12_elf.PNG|center|300px]]<br />
* A message of warning will appear, don't worry and click OK. If the source files are not displayed correctly open the configuration file (''PE_Multilink_CyclonePro.ini'') before loading the file s12.elf. Push Run (or press F5 on the keyboard) to start the application.<br />
<br />
Note: If your version of HIWAVE does not recognize the board is likely that the problem is related to the version of the dll ''peosbdmv1.dll", in the folder ''C:\Programmi\Freescale\CWS12v5.1\Prog''. Please, update the dll installing the service pack named ''CW12_V5_1_HCS12_G240_SP.exe'' or replacing the old dll with the new one provided by the latest P&E drivers.</div>Erikaddshttps://erika.tuxfamily.org/wiki/index.php?title=A_quick_tutorial_on_how_to_create,_compile_and_debug_an_application_for_Freescale_S12GA quick tutorial on how to create, compile and debug an application for Freescale S12G2011-12-12T17:32:22Z<p>Erikadds: </p>
<hr />
<div>Requirements: <br />
* Install the Freescale CodeWarrior IDE and the compiler '''CWS12v5.1'''<br />
** The Windows version of the IDE (that ocntains the compiler) can be downloaded from the following site (please note that the site requires registration): [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=CW-SUITE-SPECIAL&fpsp=1&tab=Design_Tools_Tab HCS12_CODEWARRIOR_V5.1]<br />
** Install the software in your desired location (every path without blank spaces is a recommended path, for example: ''C:\Programmi\Freescale\CWS12v5.1'').<br />
* Create a project for RT-Druid. <br />
** First enter the compiler path in RT-Druid. In the menu at the top, under ''Windows - Preferences - RT-Druid - Oil - Freescale S12'', enter the path where you installed the compiler as shown in the figure.<br />
[[image:compiler_preferences.PNG|center|300px]]<br />
** Then, select ''File - New - RT_Druid ILO and C / C + + project'' to create a new project.<br />
[[image:new_s12g_project.PNG|center|300px]]<br />
** Enter the name of the project (for example: ''s12_cw_task_demo'') and click on ''Next'' to specify a template.<br />
[[image:project_name.PNG|center|300px]]<br />
** Choose the ''Monostack TASK demo'' as shown in the figure and click on the ''Finish'' button.<br />
[[image:task_demo.PNG|center|300px]]<br />
** To use a selected revision of the kernel for project building, right-click on the project name and open the ''Properties'' window. Then select ''Erika files location'' and click to ''Configure workspace Settings'' to set the EE kernel location path for the IDE or choose another option.<br />
[[image:ee_path.PNG|center|300px]]<br />
** Now you can compile all the files of the project. To do this, simply right-click on the project name and select ''Build Project''.<br />
[[image:build_s12g.PNG|center|300px]]<br />
** If the compilation has been successfully completed the executable file, named “s12.elf”, should be present inside the Debug folder in the project tree.<br />
[[image:build_success.PNG|center|300px]]<br />
* Execute the application on the S12G micro-controller. The USB drivers for the '''TWRS12G128''' board should be already installed, otherwise follow the installation procedure described in the user manual of the board. Move the power jumpers in the right position and connect the board with the USB cable (for more info see the manual of the board). Then connect the board and your PC using a serial communication cable (please note that you may need a USB-serial converter if your PC hasn't a DB9 connector).<br />
** Copy the project path from the project properties as shown in the figure (the project path is needed to upload the executable file ''s12.elf'' in the debugger).<br />
[[image:project_path.PNG|center|300px]]<br />
** Open the Freescale debugger named HIWAVE, launching the executable “hiwave.exe” located in the “Prog” folder under the installation directory of the compiler (for example: C:\Programmi\Freescale\CWS12v5.1\Prog).<br />
[[image:hiwave.PNG|center|300px]]<br />
** Board selection. Under the menu “Component” select ''Set Connection''. In the menu choose ''HC12'', ''P&E Multilink/Cyclone Pro'' in the combo boxes and click OK.<br />
[[image:pe.PNG|center|300px]]<br />
** From the HC12MultilinkCyclonePro menu, choose ''Load ...'' and upload the executable file ''s12.elf'' located in the Debug folder inside the project. <br />
Check the box ''Automatically erase and program into FLASH and EEPROM'' and click ''Open'' (see image below).<br />
[[image:hiwave_s12_elf.PNG|center|300px]]<br />
** A message of warning will appear, don't worry and click OK. If the source files are not displayed correctly open the configuration file (''PE_Multilink_CyclonePro.ini'') before loading the file s12.elf. Push Run (or press F5 on the keyboard) to start the application.<br />
<br />
Note: If your version of HIWAVE does not recognize the board is likely that the problem is related to the version of the dll ''peosbdmv1.dll", in the folder ''C:\Programmi\Freescale\CWS12v5.1\Prog''. Please, update the dll installing the service pack named ''CW12_V5_1_HCS12_G240_SP.exe'' or replacing the old dll with the new one provided by the latest P&E drivers.</div>Erikadds