Tutorial: Building a Mico32 platform for FPG-EYE
From ErikaWiki
This section explains how to build a configuration file for FPG-EYE's fpga from a source platform with binary camera. This example is based on the platform ERIKA Enterprise and RT-Druid SVN Access. The MSB file project is located in the directory: ee/trunk/ee/examples/mico32/demo/platforms/camera_50/msb/, while the ispLever file project is located in the directory: 'ee/examples/mico32/demo/platforms/camera_50/isplever/
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Import platform project in MSB Ide
Launch MSB software, and click on MSB Perspective button (as the following figure):
Open the Open Platform form by selecting the File->Open Platform menu item:
Click the Browse button and load the file camera_50.msb from the repository copy:
The platform's architecture is visible under Sources in Project window:
Note: Do not to make any changes to the platform. And finally, generate the platform source by selecting the Run Generator menu item:
The mico32 platform Verilog source is generated. To use the platform in FPG-EYE, the source code must be compiled in binary format. The next session explain about how to compile the Verilog code for FPGA configuration file.
Import hardware platform project in ispLever Ide
Open ispLever Ide and select Open Project under File menu:
Load camera_50.msb from the repository copy:
The hardware project structure is visible under Sources in the Project window. Ensure that camera_50_wrapper.v is selected and active:
Before compiling the ispLever project, there are two more steps to perform (refer sections below).
Importing camera_component_mod.ngo in the ispLever
The component camera installed in the platform camera_50 is a binary version. So it is necessary to import in the ispLever the netlist of the camera. To do this, move the file camera_component_mod.ngo, from the packet camera to the ispLever project directory.
Importing meminit_ebr.mem bootloader file in the ispLever
The file meminit_ebr.mem is a compiled file. It is the program bootloader which would be placed in the ebr non volatile memory. For the bootloader reference guide, refer section mico32_bootloader. Move this file from the packet camera to the ispLever project directory.
Build the platform with ispLever
On Processes of current source click and select Generate Data File (JEDEC) then right click and select Force :
When the process is complete the file the FPGA configuration file JEDEC is ready to use.
The last step is download the JEDEC file into FPG-EYE. Please follow the Programming the FPG-EYE board istructions.
