Tutorial: Building a Mico32 platform for FPG-EYE

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This page explains how to build a configuration file for FPG-EYE's fpga from a source platform with binary camera. To do that you neead a local copy of Erika repopsitory,follow ERIKA_Enterprise_and_RT-Druid_SVN_Access page's instructions to get that.

Import platform project in LatticeMico System IDE

Launch LatticeMico System software, and click on MSB Perspective button (as the following figure):

MSB button

Open the Open Platform form by selecting the File->Open Platform menu item:

Open MSB platform

Click the Browse button and load ee/trunk/ee/examples/mico32/demo/platforms/camera_debug_50/msb/soc/camera_debug_50.msb file inside Erika repository local copy:

Select camera_50.msb

The platform's architecture is visible under Sources in Project window:

Select camera_50.msb platform architecture

Note: You don't need to make any changes to the platform. And finally, generate the platform source by selecting the Run Generator menu item:

Clicking on Run Generator we have the platform source

The mico32 platform's Verilog source is generated. To use this platform in FPG-EYE, the source code must be compiled in binary format. The next session explains how to compile the Verilog platform's code with ispLEVER tool.

Import hardware platform project in ispLever IDE

Open ispLEVER and select Open Project under File menu:

Open project from ispLever

Load ee/examples/mico32/demo/platforms/camera_debug_50/isplever/camera_debug_50.syn inside Erika repository local copy:

Load camera_50.msb

The hardware project structure is visible under Sources in Project window. Ensure that camera_50_wrapper.v is selected and active:

ispLever project structure

Before compiling the ispLever project, there are two more steps to perform (refer sections below).

Importing camera_component_mod.ngo in the ispLever

The component camera installed in the platform camera_50 is a binary version. So it is necessary to import in the ispLever the netlist of the camera. To do this, copy the file camera_component_mod.ngo, from the FPG-EYE Software Packet to the ispLever project directory.

camera_component_mod.ngo in ispLever project directory

Importing meminit_ebr.mem bootloader file in the ispLever

The file meminit_ebr.mem is a compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section mico32_bootloader. Copy this file from the FPG-EYE Software Packet to the ispLever project directory.

meminit_ebr.mem in ispLever project directory

Build the platform with ispLever

On Processes of current source click and select Generate Data File (JEDEC) then right click and select Force :

Force from Generate Data File (JEDEC) menu

When the process is complete the file the FPGA configuration file JEDEC is ready to use.

Generate Data File (JEDEC)

Programming the platform on FPG-EYE board

The last step is download the JEDEC file into FPG-EYE. Please follow the Programming the FPG-EYE board istructions.

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